PIC16CR74ESLASHSP datasheet(45/172 Pages) MICROCHIP

45 / 172 page

DS21993C-page 43

PIC16CR7X

5.0

TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Additional information on the Timer0 module is

available in the “PIC® Mid-Range MCU Family

Reference Manual” (DS33023).

Figure 5-1 is a block diagram of the Timer0 module and

the prescaler shared with the WDT.

Timer0

operation

controlled

through

the

OPTION_REG register (Register 5-1 on the following

page). Timer mode is selected by clearing bit T0CS

(OPTION_REG<5>). In Timer mode, the Timer0 mod-

ule will increment every instruction cycle (without pres-

caler). If the TMR0 register is written, the increment is

inhibited for the following two instruction cycles. The

user can work around this by writing an adjusted value

to the TMR0 register.

Counter mode is selected by setting bit T0CS

(OPTION_REG<5>). In Counter mode, Timer0 will

increment, either on every rising or falling edge of pin

RA4/T0CKI. The incrementing edge is determined by

the

Timer0

Source

Edge

Select

bit

T0SE

(OPTION_REG<4>). Clearing bit T0SE selects the ris-

ing edge. Restrictions on the external clock input are

discussed in detail in Section 5.2 “Using Timer0 with

an External Clock”.

The prescaler is mutually exclusively shared between

the Timer0 module and the Watchdog Timer. The

prescaler is not readable or writable. Section 5.3

“Prescaler” details the operation of the prescaler.

5.1

Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h. This overflow sets bit

TMR0IF (INTCON<2>). The interrupt can be masked

by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF

must be cleared in software by the Timer0 module

Interrupt Service Routine, before re-enabling this inter-

rupt. The TMR0 interrupt cannot awaken the processor

from Sleep, since the timer is shut-off during Sleep.

FIGURE 5-1:

BLOCK DIAGRAM OF THE TIMER0 MODULE AND PRESCALER

RA4/T0CKI

T0SE

CLKOUT (= FOSC/4)

SYNC

Cycles

TMR0 Reg

8-bit Prescaler

8-to-1 MUX

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

PSA

WDT Enable bit

Data Bus

Set Flag bit TMR0IF

on Overflow

PSA

T0CS

PRESCALER

PIC16CR74E/SP Datasheet(PDF) 45 Page - Microchip Technology

PIC16CR74E/SP Datasheet(HTML) 45 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL