PIC16CR74ESLASHSP datasheet(68/172 Pages) MICROCHIP

68 / 172 page

PIC16CR7X

DS21993C-page 66

9.3.1.1

Addressing

Once the SSP module has been enabled, it waits for a

Start condition to occur. Following the Start condition,

the 8-bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match, and the BF

and SSPOV bits are clear, the following events occur:

The SSPSR register value is loaded into the

SSPBUF register.

The Buffer Full bit, BF is set.

An ACK pulse is generated.

SSP Interrupt Flag bit, SSPIF (PIR1<3>) is set

(interrupt is generated if enabled) – on the falling

edge of the ninth SCL pulse.

In 10-bit Address mode, two address bytes need to be

received by the slave (Figure 9-7). The five Most Sig-

nificant bits (MSbs) of the first address byte specify if

this is a 10-bit address. Bit R/W (SSPSTAT<2>) must

specify a write so the slave device will receive the sec-

ond address byte. For a 10-bit address, the first byte

would equal ‘1111 0 A9 A8 0’, where A9 and A8 are

the two MSbs of the address.

The sequence of events for 10-bit address is as

follows, with steps 7-9 for slave-transmitter:

Receive first (high) byte of address (bits SSPIF,

BF, and bit UA (SSPSTAT<1>) are set).

Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

Receive second (low) byte of address (bits

SSPIF, BF and UA are set).

Update the SSPADD register with the first (high)

byte of address, if match releases SCL line, this

will clear bit UA.

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

Receive Repeated Start condition.

Receive first (high) byte of address (bits SSPIF

and BF are set).

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

TABLE 9-2:

DATA TRANSFER RECEIVED BYTE ACTIONS

9.3.1.2

Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register.

When the address byte overflow condition exists, then

no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF (SSPSTAT<0>) is

set, or bit SSPOV (SSPCON<6>) is set. This is an error

condition due to the user’s firmware.

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-

ware. The SSPSTAT register is used to determine the

status of the byte.

Status Bits as Data

Transfer is Received

SSPSR

→ SSPBUF

Generate ACK

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

SSPOV

Yes

Note:

Shaded cells show the conditions where the user software did not properly clear the overflow condition.

PIC16CR74E/SP Datasheet(PDF) 68 Page - Microchip Technology

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