PIC16CR74ESLASHSP datasheet(84/172 Pages) MICROCHIP

84 / 172 page

PIC16CR7X

DS21993C-page 82

TABLE 10-9:

REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

10.4.2

USART SYNCHRONOUS SLAVE

RECEPTION

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the Sleep

mode. Bit SREN is a “don’t care” in Slave mode.

If receive is enabled by setting bit CREN prior to the

SLEEP

instruction, then a word may be received during

Sleep. On completely receiving the word, the RSR reg-

ister will transfer the data to the RCREG register and if

enable bit RCIE bit is set, the interrupt generated will

wake the chip from Sleep. If the global interrupt is

enabled, the program will branch to the interrupt vector

(0004h).

Follow these steps when setting up a Synchronous

Slave Reception:

Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

If interrupts are desired, set enable bit RCIE.

If 9-bit reception is desired, set bit RX9.

To enable reception, set enable bit CREN.

Flag bit RCIF will be set when reception is

complete and an interrupt will be generated, if

enable bit RCIE was set.

Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

Read the 8-bit received data by reading the

RCREG register.

If any error occurred, clear the error by clearing

bit CREN.

If using interrupts, ensure that GIE and PEIE in

the INTCON register are set.

TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

Resets

0Bh, 8Bh,

10Bh,18Bh

INTCON

GIE

PEIE

TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF TMR1IF

0000 0000

18h

RCSTA

SPEN

RX9

SREN

CREN

—

FERR

OERR

RX9D

0000 000x

19h

TXREG

USART Transmit Data Register

0000 0000

8Ch

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE TMR2IE TMR1IE

0000 0000

98h

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

99h

SPBRG Baud Rate Generator Register

0000 0000

Legend:

= unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

Note

Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices; always maintain these bits clear.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

Resets

0Bh, 8Bh,

10Bh,18Bh

INTCON

GIE

PEIE

TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

18h

RCSTA

SPEN

RX9

SREN

CREN

—

FERR

OERR

RX9D

0000 000x

1Ah

RCREG

USART Receive Data Register

0000 0000

8Ch

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

98h

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

99h

SPBRG

Baud Rate Generator Register

0000 0000

Legend:

x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

Note

Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices, always maintain these bits clear.

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