PIC16CR74ESLASHSP datasheet(70/172 Pages) MICROCHIP

70 / 172 page

PIC16CR7X

DS21993C-page 68

9.3.2

MASTER MODE

Master mode of operation is supported in firmware

using interrupt generation on the detection of the Start

and Stop conditions. The Stop (P) and Start (S) bits are

cleared from a Reset or when the SSP module is dis-

abled. The Stop (P) and Start (S) bits will toggle based

on the Start and Stop conditions. Control of the I2C bus

may be taken when the P bit is set, or the bus is Idle

and both the S and P bits are clear.

In Master mode, the SCL and SDA lines are manipu-

lated by clearing the corresponding TRISC<4:3> bit(s).

The output level is always low, irrespective of the

value(s) in PORTC<4:3>. So when transmitting data, a

‘1’ data bit must have the TRISC<4> bit set (input) and

a ‘0’ data bit must have the TRISC<4> bit cleared (out-

put). The same scenario is true for the SCL line with the

TRISC<3> bit. Pull-up resistors must be provided

externally to the SCL and SDA pins for proper

operation of the I2C module.

The following events will cause SSP Interrupt Flag bit,

SSPIF, to be set (SSP Interrupt will occur if enabled):

• Start condition

• Stop condition

• Data transfer byte transmitted/received

Master mode of operation can be done with either the

Slave mode Idle (SSPM3:SSPM0 = 1011), or with the

Slave active. When both Master and Slave modes are

enabled, the software needs to differentiate the

source(s) of the interrupt.

9.3.3

MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions, allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the SSP

module is disabled. The Stop (P) and Start (S) bits will

toggle based on the Start and Stop conditions. Control

of the I2C bus may be taken when bit P (SSPSTAT<4>)

is set, or the bus is Idle and both the S and P bits clear.

When the bus is busy, enabling the SSP Interrupt will

generate the interrupt when the Stop condition occurs.

In Multi-Master operation, the SDA line must be moni-

tored to see if the signal level is the expected output

level. This check only needs to be done when a high

level is output. If a high level is expected and a low level

is present, the device needs to release the SDA and

SCL lines (set TRISC<4:3>). There are two stages

where this arbitration can be lost, these are:

• Address Transfer

• Data Transfer

When the slave logic is enabled, the slave continues to

receive. If arbitration was lost during the address trans-

fer stage, communication to the device may be in

progress. If addressed, an ACK pulse will be gener-

ated. If arbitration was lost during the data transfer

stage, the device will need to retransfer the data at a

later time.

TABLE 9-3:

REGISTERS ASSOCIATED WITH I2C™ OPERATION

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

Resets

0Bh, 8Bh,

10Bh,18Bh

INTCON

GIE

PEIE

TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF CCP1IF TMR2IF TMR1IF

0000 0000

8Ch

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE CCP1IE TMR2IE TMR1IE

0000 0000

13h

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx

uuuu uuuu

93h

SSPADD Synchronous Serial Port (I2C™ mode) Address Register

0000 0000

14h

SSPCON

WCOL

SSPOV SSPEN

CKP

SSPM3 SSPM2 SSPM1 SSPM0

0000 0000

94h

SSPSTAT

SMP(2)

CKE(2)

D/A

R/W

0000 0000

87h

TRISC

PORTC Data Direction Register

1111 1111

Legend:

= unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in

I2C™ mode.

Note

PSPIF and PSPIE are reserved on the PIC16CR73/76; always maintain these bits clear.

Maintain these bits clear in I2C mode.

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