PIC16CR74ESLASHSP datasheet(96/172 Pages) MICROCHIP

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PIC16CR7X

DS21993C-page 94

12.4

MCLR

PIC16CR7X devices have a noise filter in the MCLR

Reset path. The filter will detect and ignore small

pulses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

The behavior of the ESD protection on the MCLR pin

has been altered from previous devices of this family.

Voltages applied to the pin that exceed its specification

can result in both MCLR Resets and excessive current

beyond the device specification during the ESD event.

For this reason, Microchip recommends that the MCLR

pin no longer be tied directly to VDD. The use of an RC

network, as shown in Figure 12-5, is suggested.

FIGURE 12-5:

RECOMMENDED MCLR

CIRCUIT

12.5

Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.2V-1.7V). To take

advantage of the POR, tie the MCLR pin to VDD as

described in Section 12.4 “MCLR”. A maximum rise

time for VDD is specified. See the Electrical Specifica-

tions for details.

When the device starts normal operation (exits the

Reset condition), device operating parameters (volt-

age, frequency, temperature,...) must be met to ensure

operation. If these conditions are not met, the device

must be held in Reset until the operating conditions are

met. For additional information, refer to Application

Note AN607, “Power-up Trouble Shooting” (DS00607).

12.6

Power-up Timer (PWRT)

The Power-up Timer provides a fixed 72 ms nominal

time-out on power-up only from the POR. The Power-

up Timer operates on an internal RC oscillator. The

chip is kept in Reset as long as the PWRT is active. The

PWRT’s time delay allows VDD to rise to an acceptable

level. A Configuration bit is provided to enable/disable

the PWRT.

The power-up time delay will vary from chip-to-chip,

due to VDD, temperature and process variation. See

DC parameters for details (TPWRT, parameter #33).

12.7

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024 oscil-

lator cycles (from OSC1 input) delay after the PWRT

delay is over (if enabled). This helps to ensure that the

crystal oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset, or wake-up from

Sleep.

12.8

Brown-out Reset (BOR)

The Configuration bit, BODEN, can enable or disable

the Brown-out Reset circuit. If VDD falls below VBOR

(parameter D005, about 4V) for longer than TBOR

(parameter #35, about 100

μS), the brown-out situation

will reset the device. If VDD falls below VBOR for less

than TBOR, a Reset may not occur.

Once the brown-out occurs, the device will remain in

Brown-out Reset until VDD rises above VBOR. The

Power-up Timer then keeps the device in Reset for

TPWRT (parameter #33, about 72 mS). If VDD should fall

below VBOR during TPWRT, the Brown-out Reset pro-

cess will restart when VDD rises above VBOR, with the

Power-up Timer Reset. The Power-up Timer is always

enabled when the Brown-out Reset circuit is enabled,

regardless of the state of the PWRT Configuration bit.

12.9

Time-out Sequence

On power-up, the time-out sequence is as follows: the

PWRT delay starts (if enabled) when a POR Reset

occurs. Then, OST starts counting 1024 oscillator

cycles when PWRT ends (LP, XT, HS). When the OST

ends, the device comes out of Reset.

If MCLR is kept low long enough, all delays will expire.

Bringing MCLR high will begin execution immediately.

This is useful for testing purposes or to synchronize

more than one PIC16CR7X device operating in

parallel.

Table 12-5 shows the Reset conditions for the

STATUS, PCON and PC registers, while Table 12-6

shows the Reset conditions for all the registers.

0.1

μF

1 k

Ω (or greater)

(optional, not critical)

VDD

MCLR

PIC16CR7X

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