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PIC16CR74E/SP Datasheet(PDF) 46 Page - Microchip Technology

Part # PIC16CR74E/SP
Description  28/40-Pin, 8-Bit CMOS ROM Microcontrollers
PDF  172 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16CR74E/SP Datasheet(HTML) 46 Page - Microchip Technology

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PIC16CR7X
DS21993C-page 44
© 2007 Microchip Technology Inc.
5.2
Using Timer0 with an External
Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
REGISTER 5-1:
OPTION_REG:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RBPU: PORTB Pull-up Enable bit (see Section 2.2.2.2 “OPTION_REG Register”)
bit 6
INTEDG: Interrupt Edge Select bit (see Section 2.2.2.2 “OPTION_REG Register”)
bit 5
T0CS: TMR0 Clock Source Select bit
1
= Transition on T0CKI pin
0
= Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1
= Increment on high-to-low transition on T0CKI pin
0
= Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1
= Prescaler is assigned to the WDT
0
= Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value
TMR0 Rate
WDT Rate
Note:
To avoid an unintended device Reset, the instruction sequences shown in Example 5-1 and Example 5-2
must be executed when changing the prescaler assignment between Timer0 and the WDT. This sequence
must be followed even if the WDT is disabled.



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