PIC16CR74ESLASHSP datasheet(67/172 Pages) MICROCHIP

67 / 172 page

DS21993C-page 65

PIC16CR7X

9.3

SSP I2C™ Operation

The SSP module in I2C mode fully implements all slave

functions except general call support, and provides

interrupts on Start and Stop bits in hardware to facilitate

firmware implementations of the master functions. The

SSP module implements the standard mode specifica-

tions as well as 7-bit and 10-bit addressing.

Two pins are used for data transfer. These are the RC3/

SCK/SCL pin, which is the clock (SCL), and the RC4/

SDI/SDA pin, which is the data (SDA). The user must

configure these pins as inputs or outputs through the

TRISC<4:3> bits.

The SSP module functions are enabled by setting SSP

enable bit SSPEN (SSPCON<5>).

FIGURE 9-5:

SSP BLOCK DIAGRAM

(I2C™ MODE)

The SSP module has five registers for I2C operation.

These are the:

• SSP Control Register (SSPCON)

• SSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• SSP Shift Register (SSPSR) – Not directly

accessible

• SSP Address Register (SSPADD)

The SSPCON register allows control of the I2C opera-

tion. Four mode selection bits (SSPCON<3:0>) allow

one of the following I2C modes to be selected:

•I2C Slave mode (7-bit address)

•I2C Slave mode (10-bit address)

•I2C Slave mode (7-bit address), with Start and

Stop bit interrupts enabled to support Firmware

Master mode

•I2C Slave mode (10-bit address), with Start and

Stop bit interrupts enabled to support Firmware

Master mode

•I2C Start and Stop bit interrupts enabled to

support Firmware Master mode, Slave is Idle

Selection of any I2C mode with the SSPEN bit set,

forces the SCL and SDA pins to be open drain, pro-

vided these pins are programmed to inputs by setting

the appropriate TRISC bits. Pull-up resistors must be

provided externally to the SCL and SDA pins for proper

operation of the I2C module.

Additional information on SSP I2C operation can be

found in the “PIC® Mid-Range MCU Family Reference

Manual” (DS33023).

9.3.1

SLAVE MODE

In Slave mode, the SCL and SDA pins must be config-

ured as inputs (TRISC<4:3> set). The SSP module will

override the input state with the output data when

required (slave-transmitter).

When an address is matched, or the data transfer after

an address match is received, the hardware automati-

cally will generate the Acknowledge (ACK) pulse, and

then load the SSPBUF register with the received value

currently in the SSPSR register.

There are certain conditions that will cause the SSP

module not to give this ACK pulse. They include (either

or both):

The Buffer Full bit BF (SSPSTAT<0>) was set

before the transfer was received.

The overflow bit SSPOV (SSPCON<6>) was set

before the transfer was received.

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF (PIR1<3>) is set.

Table 9-2 shows what happens when a data transfer

byte is received, given the status of bits BF and

SSPOV. The shaded cells show the condition where

user software did not properly clear the overflow condi-

tion. Flag bit BF is cleared by reading the SSPBUF

The SCL clock input must have a minimum high and

low for proper operation. The high and low times of the

I2C specification, as well as the requirements of the

SSP module, are shown in timing parameter #100 and

parameter #101.

Read

Write

SSPSR Reg

Match Detect

SSPADD Reg

Start and

Stop bit Detect

SSPBUF Reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPSTAT Reg)

RC3/SCK/SCL

RC4/

Shift

Clock

MSb

SDI/

LSb

SDA

PIC16CR74E/SP Datasheet(PDF) 67 Page - Microchip Technology

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