PCF8534 datasheet(14/40 Pages) PHILIPS

14 / 40 page

PCF8534_0

Preliminary datasheet

Rev. 00.05 — 20 February 2007

14 of 40

NXP Semiconductors

PCF8534

Universal LCD driver for low multiplex rates

6.5 Oscillator

6.5.1 Internal clock

The internal logic and the LCD drive signals of the PCF8534 are timed either by the

built-in oscillator or from an external clock. When the internal oscillator is used, you must

connect pad OSC to VSS. In this event, the output from pad CLK provides the clock signal

for cascaded PCF8534’s in the system. After power-up, SDA must be HIGH to guarantee

that the clock starts.

6.5.2 External clock

The condition for external clock is made by tying pad OSC to VDD; pad CLK then becomes

the external clock input.

The clock frequency (fCLK) determines the LCD frame frequency.

A clock signal must always be supplied to the device; removing the clock may freeze the

LCD in a DC state.

6.6 Timing

The timing of the PCF8534 organizes the internal data flow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs. In

cascaded applications the synchronization signal (SYNC) maintains the correct timing

relationship between the PCF8534’s in the system. The timing also generates the LCD

frame frequency which it derives as an integer division of the clock frequency

(see Table 6). The frame frequency is a fixed division of the internal clock or of the

frequency applied to pad CLK when an external clock is used.

6.7 Display register

The display latch holds the display data while the corresponding multiplex signals are

generated. There is a one-to-one relationship between the data in the display latch, the

LCD segment outputs and one column of the display RAM.

6.8 Segment outputs

The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected

directly to the LCD. The segment output signals are generated in accordance with the

multiplexed backplane signals and with data resident in the display latch. When less than

60 segment outputs are required the unused segment outputs must be left open-circuit.

6.9 Backplane outputs

The LCD drive section includes four backplane outputs BP0 to BP3 which must be

connected directly to the LCD. The backplane output signals are generated in accordance

with the selected LCD drive mode. If less than four backplane outputs are required the

unused outputs can be left open-circuit. In the 1:3 multiplex drive mode BP3 carries the

same signal as BP1, therefore these two adjacent outputs can be tied together to give

enhanced drive capabilities. In the 1:2 multiplex drive mode BP0 and BP2, BP1 and BP3

respectively carry the same signals and may also be paired to increase the drive

capabilities. In the static drive mode the same signal is carried by all four backplane

outputs and they can be connected in parallel for very high drive requirements.

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