PCF8534 datasheet(25/40 Pages) PHILIPS

25 / 40 page

PCF8534_0

Preliminary datasheet

Rev. 00.05 — 20 February 2007

25 of 40

NXP Semiconductors

PCF8534

Universal LCD driver for low multiplex rates

only one device need to be through-plated to the backplane electrodes of the display. The

other PCF8534’s of the cascade contribute additional segment outputs but their

backplane outputs are left open-circuit (see Figure 17).

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF8534’s. This synchronization is guaranteed after the power-on reset. The only time

that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in

adverse electrical environments, or by the definition of a multiplex mode when PCF8534’s

with different SA0 levels are cascaded). SYNC is organized as an input / output pad; the

output selection being realized as an open-drain driver with an internal pull-up resistor. A

PCF8534 asserts the SYNC line at the onset of its last active backplane signal and

monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is

restored by the first PCF8534 to assert SYNC. The timing relationship between the

backplane waveforms and the SYNC signal for the various drive modes of the PCF8534

are shown in Figure 18.

The contact resistance between the SYNC pads of cascaded devices must be controlled.

If the resistance is too high then the device will not be able to synchronize properly.

Table 18 shows the limiting values for contact resistance.

Table 18.

SYNC contact resistance

Number of devices

Maximum contact resistance

6000

3 to 5

2200

6 to 10

1200

11 to 16

700

PCF8534 Datasheet(PDF) 25 Page - NXP Semiconductors