PCF8534 datasheet(29/40 Pages) PHILIPS

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PCF8534_0

Preliminary datasheet

Rev. 00.05 — 20 February 2007

29 of 40

NXP Semiconductors

PCF8534

Universal LCD driver for low multiplex rates

[1]

LCD outputs are open circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive.

[2]

Not tested, design spec only.

[3]

Outputs measured individually and sequentially.

10. Dynamic characteristics

IOH1

High-level output

current pad CLK

VOH = 4.6 V; VDD = 5 v

−1-

IOL2

Low-level output

current pad SDA

VOL = 0.4 V; VDD = 5 V

IL1

leakage current pads

SA0, A0 to A2, CLK,

SDA and SCL

V1 = VDD or VSS

−1-

μA

IL2

leakage current pad

OSC

V1 = VDD

−1-

μA

input capacitance

[2] --7

VPOR

power on reset

voltage level

1.01.3

1.6V

LCD outputs

VBP

DC voltage

component on pads

BP0 to BP3

CBP = 35 nF

−100

+100

DC voltage

component on pads

S0 to S59

CS = 5 nF

−100

+100

RBP

output resistance at

pads BP0 to BP3

VLCD = 5 V

[3] -1.5

output resistance at

pads S0 to S59

VLCD = 5 V

[3] -6.0

13.5

Table 20.

Static characteristics

VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; TAMB =

−40 to +85°C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 21.

Dynamic characteristics

VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; TAMB =

−40 to +85°C; unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fCLK(int)

oscillator frequency on pad CLK (internal clock)

VDD = 5 V

[1] 960

1536

3046

fCLK(ext)

oscillator frequency on pad CLK (external clock)

VDD = 5 V

797

1536

3046

tCLKH

input CLK HIGH time

130

μs

tCLKL

input CLK LOW time

130

μs

CLK rise time

---ns

CLK fall time

---ns

td(p)SYNC

SYNC propagation delay time

tSYNCL

SYNC LOW time

μs

td(PLCD)

driver delays with test loads

VLCD = 5 V

--30

μs

Timing characteristic: I2C bus

[2]

fSCL

SCL clock frequency

400

kHz

tBUF

bus free time between a stop and a start

1.3

μs

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