PCF8534 datasheet(24/40 Pages) PHILIPS

24 / 40 page

PCF8534_0

Preliminary datasheet

Rev. 00.05 — 20 February 2007

24 of 40

NXP Semiconductors

PCF8534

Universal LCD driver for low multiplex rates

[1]

Normal blinking is assumed when the multiplex rates 1:3 or 1:4 are selected.

7.10 Display controller

The display controller executes the commands identified by the command decoder. It

contains the status registers of the PCF8534 and co-ordinates their effects.

The controller is also responsible for loading display data into the display RAM as required

by the filling order.

7.11 Cascaded operation

In large display configurations, up to 16 PCF8534’s can be distinguished on the same

I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable

I2C-bus slave address (SA0). When cascaded PCF8534’s are synchronized they can

share the backplane signals from one of the devices in the cascade. Such an

arrangement is cost-effective in large LCD applications since the backplane outputs of

Table 12.

Load data pointer option 1

Description

Bits

7 bit ordinary value of 0 to 59

Table 13.

Device selected option 1

Description

Bits

3 bit binary value of 0 to 7

Table 14.

Blank select option 1 (input)

Static

1:2 MUX

Bit I

RAM bit 0

RAM bits 0 and 1

RAM bit 2

RAM bits 2 and 3

Table 15.

Blank select option 2 (output)

Static

1:2 MUX

Bit O

RAM bit 0

RAM bits 0 and 1

RAM bit 2

RAM bits 2 and 3

Table 16.

Blink option 1

Blink frequency

Bits

BF1

BF0

off

2 Hz

1 Hz

1.5 Hz

Table 17.

Blink option 2

Blink mode

Bit A

normal blinking

[1]

alteration blinking

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