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PCF8534 Datasheet(PDF) 20 Page - NXP Semiconductors |
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PCF8534 Datasheet(HTML) 20 Page - NXP Semiconductors |
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20 / 40 page ![]() PCF8534_0 © NXP B.V. 2007. All rights reserved. Preliminary datasheet Rev. 00.05 — 20 February 2007 20 of 40 NXP Semiconductors PCF8534 Universal LCD driver for low multiplex rates 7.5 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure 14. 7.6 PCF8534 I2C-bus controller The PCF8534 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8534 are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. Fig 13. System configuration mga807 SDA SCL MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER/ RECEIVER Fig 14. Acknowledgement of the I2C-bus mbc602 S START condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver SCL from master |
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