PCF8534 datasheet(15/40 Pages) PHILIPS

15 / 40 page

PCF8534_0

Preliminary datasheet

Rev. 00.05 — 20 February 2007

15 of 40

NXP Semiconductors

PCF8534

Universal LCD driver for low multiplex rates

6.10 Display RAM

The display RAM is a static 60 x 4-bit RAM which stores LCD data. A logic 1 in the RAM

bit map indicates the on-state of the corresponding LCD segment; similarly, a logic 0

indicates the off-state. There is a one-to-one correspondence between the RAM

addresses and the segment outputs, and between the individual bits of a RAM word and

the backplane outputs. The first RAM column corresponds to the 60 segments operated

with respect to backplane BP0 (see Figure 9). In multiplexed LCD applications the

segment data of the second, third and fourth column of the display RAM are

time-multiplexed with BP1, BP2 and BP3 respectively.

When display data is transmitted to the PCF8534 the display bytes received are stored in

the display RAM in accordance with the selected LCD drive mode. The data is stored as it

arrives and does not wait for the acknowledge cycle as with the commands. Depending on

the current mux mode data is stored singularly, in pairs, triplets or quadruplets. e.g. in 1:2

mux mode the RAM data is stored every second bit. To illustrate the filling order, an

example of a 7-segment numeric display showing all drive modes is given in Figure 10;

the RAM filling organization depicted applies equally to other LCD types. With reference

to Figure 10, in the static drive mode the eight transmitted data bits are placed in bit 0 of

eight successive display RAM addresses. In the 1:2 multiplex drive mode the eight

transmitted data bits are placed in bits 0 and 1 of four successive display RAM addresses.

In the 1 : 3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three

successive addresses, with bit 2 of the third address left unchanged. This last bit may, if

necessary, be controlled by an additional transfer to this address but care should be taken

to avoid overriding adjacent data because full bytes are always transmitted. In the 1:4

multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two

successive display RAM addresses.

Table 6.

LCD frame frequencies

Frame frequency

Nominal frame frequency (Hz)

CLK

-----------

Fig 9.

Display RAM bit map showing direct relationship between backplane outputs, display RAM addresses and

segment outputs, and between bits in a RAM word and backplane outputs.

PCF8534 Datasheet(PDF) 15 Page - NXP Semiconductors