TLV2548MFKB datasheet(5/41 Pages) TI

5 / 41 page

TLV2544Q, TLV2548Q, TLV2548M

3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN

SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

detailed description (continued)

serial interface

INPUT DATA FORMAT

MSB

LSB

D15–D12

D11–D0

Command

Configuration data field

Input data is binary. All trailing blanks can be filled with zeros.

OUTPUT DATA FORMAT READ CFR

MSB

LSB

D15–D12

D11–D0

Don’t care

OUTPUT DATA FORMAT CONVERSION/READ FIFO

MSB

LSB

D15–D4

D3–D0

Conversion result

Don’t care

The output data format is binary (unipolar straight binary).

binary

Zero scale code = 000h, Vcode = VREFM

Full scale code = FFFh, Vcode = VREFP – 1 LSB

control and timing

power up and initialization requirements

D Determine processor type by writing A000h to the TLV2544/48 (CS must be toggled)

D Configure the device (CS must make a high-to-low transition, then can be held low if in DSP mode; i.e.,

active FS.)

The first conversion after power up or resuming from power down is not valid.

start of the cycle:

D When FS is not used (FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle.

D When FS is used (FS is an active signal from a DSP), the falling edge of FS is the start of the cycle.

first 4-MSBs: the command register (CMR)

The TLV2544/TLV2548 have a 4-bit command set (see Table 1) plus a 12-bit configuration data field. Most of

the commands require only the first 4 MSBs, i.e., without the 12-bit data field.

NOTE:

The device requires a write CFR (configuration register) with 000h data (write A000h to the serial

input) at power up to initialize host select mode.

The valid commands are listed in Table 1.

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