TLV2544Q, TLV2548Q, TLV2548M

3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN

SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002

16

POST OFFICE BOX 655303

modes using the FIFO: modes 01, 10, 11 timing (continued)

CS

CSTART

SDI

INT

SDO

Hi-Z

FS

(DSP)

Configure

Select

Conversion #1 From Channel 2

Select

Conversion #4 From Channel 2

Read FIFO

First FIFO Read

‡‡

‡

‡

§

#1

#2

#3

#4

†

§

t(sample)

Hi-Z

Sample Times

≥ MIN t(sample)

(See Operating Characteristics)

t(sample)

t(sample)

t(sample)

¶

† Command = Configure write for mode 01, FIFO threshold = 1/2

‡ Command = Read FIFO, 1st FIFO read

§ Command = Select ch2.

¶ Minimum CS low time for select cycle is 6 SCLKs. The same amount of time is required between FS low to CSTART for proper channel decoding.

The low time of CSTART, not overlapped with CS low time, is the valid sampling time for the select cycle (see Figure 18).

Figure 11. TLV2544/TLV2548 Mode 01

µp/DSP Serial Interface (Conversions Triggered by CSTART)

CS

CSTART

SDI

INT

SDO

From Channel 0

FS

(DSP)

From Channel 3

Configure

Conversion

Conversion

Read FIFO

#1

#2

#3

#4

Top of FIFO

‡

‡

†

‡‡

‡

Read FIFO

#1

From Channel 0

Conversion

From Channel 3

Conversion

Repeat

Second FIFO Read

Repeat

First FIFO Read

§

§

§

§

§

§

§

§

† Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0–1–2–3.

‡ Command = Read FIFO

§ Use any channel select command to trigger SDI input.

Figure 12. TLV2544/TLV2548 Mode 10/11 DSP Serial Interface (Conversions Triggered by FS)