TLV2544Q, TLV2548Q, TLV2548M

3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN

SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002

24

POST OFFICE BOX 655303

= 3 V to 5.5 V, SCLK frequency = 20 MHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

EL

Integral linearity error (INL) (see Note 5)

±1.2

LSB

ED

Differential linearity error (DNL)

See Note 4

±1

LSB

Q Suffix

±2

EO

Offset error (see Note 6)

See Note 4

M Suffix, TA = 25°C

and 125

°C

–4

+6

LSB

M Suffix, TA = –55°C

–4

+6.2

Q Suffix

±1.1

±4

EFS

Full scale error (see Note 6)

See Note 4

M Suffix, TA = 25°C

and 125

°C

–4

±1.1

+6

LSB

M Suffix, TA = –55°C

–4

±1.1

+7.6

SDI = B000h

800h

(2048D)

Self-test output code (see Table 1 and

Note 7)

SDI = C000h

000h (0D)

Note 7)

SDI = D000h

FFFh

(4095D)

Internal OSC

OSC = 3 MHz to 6 MHz

3.2

4.65

t(conv)

Conversion time

External SCLK

(14

DIV)

f

SCLK

µs

t(sample) Sampling time

With a maximum of 1-k

Ω input source

impedance

600

ns

† All typical values are at TA = 25°C.

NOTES:

4. Analog input voltages greater than that applied to REFP convert as all ones (111111111111), while input voltages less than that

applied to REFM convert as all zeros (000000000000).

5. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.

6. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference

between 111111111111 and the converted output for full-scale input voltage.

7. Both the input data and the output codes are expressed in positive logic.