MPC8280 datasheet(1231/1386 Pages) FREESCALE

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ATM Transmission Convergence Layer

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

35-15

35.5

Implementation Example

Figure 35-12 shows the MPC8280 connected to two PHY devices, each containing four T1 framers. The

eight T1 bit streams are connected to the eight MPC8280 SI TDMs and routed via the SI to the eight TC

layer blocks. The eight TC layer blocks, each with its own address, are connected internally to FCC2 via

the UTOPIA 8-bit bus. Another ATM stream is managed by FCC1 via the UTOPIA 16-bit bus connected

to a SONET 155-Mbps PHY.

Figure 35-12. Example of Serial ATM Application

35.5.1

Operating the TC Layer at Higher Frequencies

The operation of the TC layer requires a minimum frequency ratio of 1:2.5 between the serial clock and

the UTOPIA clock (in Rx and Tx separately). Using the TC for serial frequencies greater than 10 MHz

requires using higher UTOPIA frequencies to preserve that ratio.

35.5.2

Programming a T1 Application

This section describes the configurations necessary to implement a T1 application using a single TC layer

block. Note that using two or more TCs requires FCC2 to work in MPHY mode. Assuming that the

FCC2

SI-2

4 channel

PHY

FCC1

UTOPIA 8-bit bus

UTOPIA 16-bit bus

DPR

SONET

155 mbps

PHY

4*1.5 mbps

8*1.5 mbps

TDMa

TDMb

TDMc

TDMd

TDMa

TDMb

TDMc

TDMd

SI-1

Framer

4 channel

PHY

4*1.5 mbps

Framer

MPC8280

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