MPC8280 datasheet(1227/1386 Pages) FREESCALE

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ATM Transmission Convergence Layer

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

35-11

35.4.2.2

TC Layer General Status Register (TCGSR)

Figure 35-9 shows the TC layer general status register (TCGSR), which records the cell delineation and

transmit FIFO status for all TC blocks.

Table 35-6 describes TCGSR fields.

35.4.3

TC Layer Cell Counters

Each TC block maintains six memory-mapped 16-bit performance cell counters that are updated during

operation and can be read by the host. If a counter overflows, it wraps back to zero and generates a

maskable interrupt. These counters are automatically cleared when read if TCMODE[CM] = 0; see

Section 35.4.1.1, “TC Layer Mode Registers 1–8 (TCMODEx).”

35.4.3.1

Received Cell Counters 1–8 (TC_RCC

This cell counter is updated whenever a received cell without HEC errors is passed to the Rx UTOPIA

FIFO.

35.4.3.2

Transmitted Cell Counters 1–8 (TC_TCC

This cell counter is updated whenever the transmission of a cell is completed.

TC4

One bit or more is set in TC4 event register.

TC5

One bit or more is set in TC5 event register.

TC6

One bit or more is set in TC6 event register.

TC7

One bit or more is set in TC7 event register.

TC8

One bit or more is set in TC8 event register.

Field CD1

CD2

CD3

CD4

CD5

CD6

CD7

CD8

—

Reset

0000_0000_0000_0000

R/W

Figure 35-9. TC Layer General Status Register (TCGSR)

Table 35-6. TCGSR Field Descriptions

Bits

Name

Description

0–7

CDx

Cell Delineation. The cell delineation state machine status of TCx.

0 Cell delineation state machine is in Hunt or Pre-Synch modes.

1 Cell delineation machine is in Synch mode.

8–15

—

Reserved

Table 35-5. TCGER Field Descriptions (continued)

Bits

Name

Description

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