MPC8280 datasheet(1228/1386 Pages) FREESCALE

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ATM Transmission Convergence Layer

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

35-12

Freescale Semiconductor

35.4.3.3

Errored Cell Counters 1–8 (TC_ECC

This cell counter is updated whenever a received errored cell (cell with header error) is discarded.

35.4.3.4

Corrected Cell Counters 1–8 (TC_CCC

This cell counter is updated whenever a received cell with a HEC single bit error is corrected. If header

single bit error correction is not enabled (TCMODE[SBC] is set), this counter is not updated. (All errored

cells are counted by the errored cell counter (ECC).)

35.4.3.5

Transmitted IDLE Cell Counters 1–8 (TC_ICC

This cell counter is updated whenever an idle cell is transmitted.

35.4.3.6

Filtered Cell Counters 1–8 (TC_FCC

This cell counter is updated whenever an idle/unassigned cell is filtered (discarded). If cell filters are not

enabled (TCMODE[CF] is cleared), this counter is not updated.

35.4.4

Programming FCC2

FCC2 is designed to work with the TC blocks. The TC blocks are located on fixed addresses on the

UTOPIA bus internally. FCC2 should be programmed to work with the TC blocks as if the TC blocks are

external PHYs located on the lowest eight (or fewer) addresses.

35.4.5

Programming and Operating the TC Layer

35.4.5.1

Receive

The TC layer receive operation is enabled by setting TCMODEx[RXEN].

The host software polls the CD bits of each enabled TC layer block to see that its receive cell delineation

state machines are synchronized. For each TC layer block that is synchronized, the host clears

TCERx[CDT]. Once all the enabled TC layer blocks are synchronized, the host terminates its initialization

routine, and the system starts normal operation.

Once a TC block gets out of synchronization, the corresponding TCGSR[CD] is cleared. This change then

causes a TCER[CDT] interrupt to the host (if enabled in the mask register—TCMRx).

On the receive path, the TC layer receives the bit stream via the SI and does the following:

1. Attempts to gain synchronization on the ATM cell boundaries by checking each byte against the

HEC calculated on the preceding 32 bits (ATM cell header candidate).

2. Once synchronized:

— Performs the descrambling function on the cell payload (if enabled)

— Performs the coset function on the HEC (if enabled)

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