MPC8280 datasheet(1230/1386 Pages) FREESCALE

1230 / 1386 page

ATM Transmission Convergence Layer

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

35-14

Freescale Semiconductor

Figure 35-10. TC Operation in FCC External Rate Mode

•

Internal Rate (Sub Rate)—The TC layer continues to request ATM cells and transmits idle cells.

TCERx[UR] interrupts can by disabled by clearing TCMODEx[URE] until a valid ATM cell is

transmitted via the internal UTOPIA bus from FCC2 to the TC layer FIFO. See Figure 35-11.

Figure 35-11. TC Operation in FCC Internal Rate Mode (Sub Rate Mode)

Operation in byte-aligned mode (TCMODE[xTBA] = 1) is required for T1/E1 mainly. In this mode, once

the TC is enabled, it waits for the first Txsyn pulse to start transmit the first byte of the first cell. This

ensures that subsequent Txsyn pulses are byte-aligned to the cell boundaries.

FCC

PHY

MPC8280

DPR

UTOPIA

2M Cell Rate

2M Serial Rate

Keep FCC FIFO full

Generate Idle Cells

cell_req

BTM

ATM Channels

Idle Cell

ATM Cell

(External Rate)

FCC

PHY

MPC8280

DPR

UTOPIA

1M Cell Sub Rate

2M Serial Rate

1M Sub Rate

Generate Cell Req

BRG

cell req

Generate Idle Cells

BTM

ATM Channels

Idle cell

ATM cell

(Internal/Sub Rate)

Write to FIFO

ATM Cells Only

MPC8280 Datasheet(PDF) 1230 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1230 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL