MPC8280 datasheet(1229/1386 Pages) FREESCALE

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ATM Transmission Convergence Layer

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

35-13

— Checks for HEC errors and corrects single HEC errors when found (again, if enabled). Cells

containing multi-bit header errors (at least 2 errors) are discarded. Idle and unassigned cells are

filtered (discarded) when detected (if the filters are enabled).

Once an ATM cell’s processing is complete, it is passed to the TC layer receive FIFO and the internal TC

layer cell counters are updated. The cell is passed from the TC layer receive FIFO via the internal UTOPIA

interface to the FCC2 receive FIFO.

An overrun condition occurs when the TC layer receive FIFO is full and the FCC is unable to read a cell

from it (via the internal UTOPIA interface) before another valid cell is received. The incoming cell is

discarded and TCER[OR] interrupt is sent to the host (if enabled in the mask register—TCMRx).

35.4.5.2

Transmit

The TC layer transmit operation is enabled by setting TCMODEx[TXEN].

The TC layer requests ATM cells for transmission via the internal UTOPIA interface. Then, when the ATM

cell is passed to the TC layer transmit block, it is stored in the TC layer transmit FIFO. When the ATM cell

is to be transmitted, it is read and processed from the TC layer transmit FIFO.

The scrambling function is performed on the ATM cell payload if TCMODEx[TPS] = 1. The ATM cell

header HEC value is calculated and the coset function is performed on the HEC if TCMODEx[TC] = 1.

The ATM cell is then sent to the PHY via the SI. Once ATM cell transmission is complete, the relevant TC

layer cell counters are updated.

When a TC layer cell counter overflows, an interrupt (TCERx[TOF]) is set (if enabled in the corresponding

TCMRx[TOF]).

The TC layer is responsible for providing the data rate required by the physical medium device (PMD).

On MPC8280 there are two ATM transmit modes. Users should refer to Section 31.2.1.5, “Transmit

External Rate and Internal Rate Modes,” for more details. The following text and figures are specific to

TC layer operation.

•

External Rate—In general, the TC would never have its transmit FIFO empty, and thus would not

need to generate idle cells. However, if the CPM is busy and if the transmit FIFO is empty, the TC

layer generates an idle cell and an underrun condition will occur. If TCMODEx[URE] = 1, the

TCERx[UR] interrupt is sent to the host (if not masked). See Figure 35-10.

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