MPC8280 datasheet(1226/1386 Pages) FREESCALE

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ATM Transmission Convergence Layer

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

35-10

Freescale Semiconductor

35.4.1.4

TC Layer Mask Register (TCMRx)

This register’s field description is identical to that of TCER (refer to Section 35.4.1.3, “TC Layer Event

Registers 1–8 (TCERx)”). Each bit that is set in TCMR enables an interrupt when the corresponding bit in

TCER is set.

35.4.2

TC Layer General Registers

The TC layer general registers are registers that are distributed to all of the TC blocks. Each TC block is

represented by specific bits. When accessing a general register each TC block is responsible for its specific

bits only.

35.4.2.1

TC Layer General Event Register (TCGER)

The TC layer general event register (TCGER), as shown in Figure 35-8, summarizes the events for all the

TC blocks. Each bit stands for an ORed event register of a TC block. Once a bit is set, it indicates that one

or more event bits are set in the corresponding TC block event register.

Table 35-5 describes TCGER fields.

EOF

Errored cells counter overflow

Set when the errored cells counter passes its maximum value.

COF

Corrected cells counter overflow

Set when the corrected cells counter passes its maximum value.

IOF

Tx Idle cells counter overflow

Set when the Tx idle cells counter passes its maximum value.

FOF

Filtered cells counter overflow

Set when the filtered cells counter passes its maximum value.

Field TC1

TC2

TC3

TC4

TC5

TC6

TC7

TC8

—

Reset

0000_0000_0000_0000

R/W

Figure 35-8. TC Layer General Event Register (TCGER)

Table 35-5. TCGER Field Descriptions

Bits

Name

Description

TC1

One bit or more is set in TC1 event register.

TC2

One bit or more is set in TC2 event register.

TC3

One bit or more is set in TC3 event register.

Table 35-4. TCER

x Field Descriptions (continued)

Bits

Name

Description

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