MPC8280 datasheet(1225/1386 Pages) FREESCALE

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ATM Transmission Convergence Layer

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

35-9

Table 35-3 describes CDSMR fields.

35.4.1.3

TC Layer Event Registers 1–8 (TCER

The TC layer event registers (TCERx), as shown in Figure 35-7, records error events for each TC block.

TCER event bits are cleared by writing ones to them.

The TCER bits are described in Table 35-4.

Table 35-3. CDSMR

x Field Descriptions

Bits

Name

Description

0–4

ALPHA

ALPHA consecutive received cells with incorrect HEC are counted by the cell delineation state

machine to pass from state SYNCH to state HUNT.

5–9

DELTA

DELTA consecutive received cells with correct HEC are counted by the cell delineation state

machine to pass from state PRESYNCH to state SYNCH.

10–15

—

Reserved

101112131415

Field

CDT

PARE

—

ROF

TOF

EOF

COF

IOF

FOF

Reset

0000_0000_0000_0000

R/W

Figure 35-7. TC Layer Event Registers (TCER

Table 35-4. TCER

x Field Descriptions

Bits

Name

Description

Overrun. Rx FIFO OverFlow.

Set when Rx FIFO is full and another complete cell is received. The cell is discarded.

Underrun. No ATM cell to transmit.

Set when the Tx FIFO is empty and the transmission of a cell is completed. An idle cell

is sent.

This interrupt is enabled only if TCMODE[URE] is set.

The idle cell header is: 0x00000001 (I.432), whose HEC is: 0x52

The idle cell payload is:0x6A (I.432).

CDT

Cell delineation toggled.

Set when the cell delineation bit (CD) in TCGSR has changed.

Misplaced Txsyn signal

Set when Txsyn is out of place. (The first Txsyn is by definition always in place.)

PARE

Parity event

Set when parity from UTOPIA to transmit is wrong.

5–9

—

Reserved

ROF

Received cell counter overflow

Set when the received cells counter passes its maximum value.

TOF

Transmitted cell counter overflow

Set when the transmitted cells counter passes its maximum value.

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