MPC8280 datasheet(1371/1386 Pages) FREESCALE

1371 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Index-17

DMA chaining mode, 9-86

DMA coherency, 9-87

DMA transfer types, 9-87

halt and error conditions, 9-87

mode registers (DMAMRx), 9-88

next descriptor address registers (DMANDARx), 9-94

source address registers (DMASARx), 9-92

status registers (DMASRx), 9-90

error handling, 9-97

interrupt and error signals, 9-97

embedded utilities, 9-100

error reporting, 9-98

illegal register access error, 9-98

parity error (PERR), 9-98

PCI bus error signals, 9-97

PCI interface, 9-98, 9-99, 9-100

system error (SERR), 9-98

in MPC8280, 9-2

initialization, 9-3

interface, 9-5

bus arbitration, 9-19

alogrithm, 9-19

master latency timer, 9-20

parking, 9-19

operation, 9-6

bus commands, 9-6

bus transactions

read and write, 9-9

termination, 9-11

error functions, 9-17

parity, 9-17

reporting, 9-18

other bus operations, 9-13

agent mode configuration access, 9-16

data streaming, 9-14

device selection, 9-13

fast back-to-back transactions, 9-14

host mode configuration access, 9-15

interrupt acknowledge, 9-17

special cycle command, 9-16

protocol fundamentals, 9-7

addressing, 9-8

basic transfer control, 9-8

bus driving and turnaround, 9-9

byte enable signals, 9-9

interrupts from, 9-4

message unit (I2O), 9-66

door bell registers, 9-68

inbound (IDR), 9-68

outbound (ODR), 9-68

I20 unit, 9-69

I20 registers, 9-77

inbound FIFO queue port register (IFQPR), 9-77

inbound message interrupt mask register (IMIMR),

9-82

inbound message interrupt status register (IMISR),

9-81

messaging unit control register (MUCR), 9-83

outbound FIFO queue port register (OFQPR), 9-78

outbound message interrupt mask register

(OMIMR), 9-80

outbound message interrupt status register

(OMISR), 9-79

queue base address register (QBAR), 9-84

inbound FIFOs, 9-70

PCI configuration identification, 9-70

inbound FIFOs

Free_FIFO head pointer register (IFHPR), 9-71

Free_FIFO tail pointer register (IFTPR), 9-71

post_FIFO head pointer register (IPHPR), 9-72

post_FIFO tail pointer register (IPTPR), 9-72

message registers, 9-66

inbound message registers (IMRx), 9-66

outbound message registers (OMRx), 9-67

outbound FIFOs, 9-74

free_FIFO head pointer register (OFHPR), 9-74

free_FIFO tail pointer register (OFTPR), 9-74

post_FIFO head pointer register (OPHPR), 9-75

post_FIFO head pointer register (OPTPR), 9-75

PCI parity operation, 9-18

SDMA interface, 9-3

signals, 9-3

single beat read example, 9-10

single beat write example, 9-11

structure, 9-2

target-initiated terminations, 9-12

PDATx (port data) registers, 41-2

PDIRx (port data direction registers), 41-3

PDTEA (SDMA 60x bus transfer error address register), 19-4

PDTEM (SDMA 60x bus transfer error MSNUM register),

19-4

PISCR (periodic interrupt status and control register), 4-47

PITC (periodic interrupt timer count register), 4-48

PITR (periodic interrupt timer register), 4-49

PLL pins,, 10-5

PLPRCR,, 10-7

PODRx (port open-drain registers), 41-1

PORESET,, 6-14

Power consumption

FCCs, 30-22

SCCs, 20-25

PPAR (port pin assignment register), 41-4

PPC_ACR (60x bus arbiter configuration register), 4-29

PPC_ALRH (60x bus arbitration high-level register), 4-30

MPC8280 Datasheet(PDF) 1371 Page - Freescale Semiconductor, Inc

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