MPC8280 datasheet(1367/1386 Pages) FREESCALE

1367 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Index-13

IMA frame overview, 34-5

introduction, 34-4

root table data structures, 34-25

software interface and requirements, 34-58

initialization procedure, 34-59

software model, 34-58

software procedures, 34-62

end-to-end channel signalling, 34-74

transmit, 34-74

group start-up, 34-63

as initiator (TX), 34-64

as responder (RX), 34-65

IDCR operation, 34-73

IDCR mode group activation, 34-74

start-up, 34-73

link addition, 34-65

Rx steps, 34-65

TX parameters, 34-66

link receive deactivation procedure, 34-68

link receive reactivation, 34-69

link removal, 34-67

Rx steps, 34-67

TX parameters, 34-68

receive event response, 34-70

receive link start-up procedure, 34-62

test pattern, 34-72

as initiator (NE), 34-72

as responder (FE), 34-72

transmit event response, 34-70

transmit ICP cell signalling, 34-62

TRL on-the-fly change, 34-69

software responsibilities, 34-59

failure alarms, 34-61

general operation, 34-60

group symmetry control, 34-61

ICP end-to-end channel transmission, 34-61

link addition and slow recovery (LASR), 34-61

performance parameter measurement and reporting,

34-62

receive group state machine control, 34-60

receive link state machine control, 34-60

SNMP MIBs, 34-62

system definition, 34-59

test pattern control, 34-62

transmit group state machine control, 34-61

transmit link state machine control, 34-60

IMMR (internal memory map register), 4-36

Input/output port memory map, 3-9

Instruction field conventions, 1-lxxxviii

Instruction queue (IQ), 2-5

Instruction timing overview, 2-26

Instruction unit, 2-5

Integer unit (IU), 2-6

Interrupts

ATM interrupt queues, 31-82

RISC timer tables

interrupt handling, 14-31

SCC interrupt handling, 20-16

Inverse Multiplexing for ATM (IMA)

see IMA, 34-1

JTAG implementation, 1-5

L_TESCR1 (local bus transfer error status and control

L_TESCR2 (local bus transfer error status and control

L_TESCRx (local bus error status and control registers),

11-33

LCL_ACR (local bus arbiter configuration register), 4-31

LCL_ALRH (local bus arbitration high-level register), 4-32

LCL_ALRL (local bus arbitration low-level register), 4-33

LDTEA (SDMA local bus transfer error address register),

19-4

LDTEM (SDMA local bus transfer error MSNUM register),

19-4

Load/store unit (LSU), 2-7

Loopback mode, 15-7

LSDMR (local bus SDRAM mode register), 11-24

LSRT (local bus-assigned SDRAM refresh timer) register,

11-32

LURT (local bus-assigned UPM refresh timer) register, 11-30

MCCE (MCC event) register, 29-37

MCCFx (MCC configuration registers), 29-33

MCCM (MCC mask) register, 29-37

MDR (memory data register), 11-28

Memory controller

address checking, 11-7

address latch enable (ALE), 11-10

address space checking, 11-7

architecture overview, 11-4

atomic bus operation, 11-9

basic architecture, 11-4

basic operation, 11-7

boot chip-select operation, 11-62

controlling the timing of GPL1, GPL2, and CSx, 11-69

CSx timing example, 11-69

delayed read, 11-9

MPC8280 Datasheet(PDF) 1367 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1367 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL