MPC8280 datasheet(1365/1386 Pages) FREESCALE

1365 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Index-11

General-purpose signals, 11-76

GFMR (general FCC mode register), 30-3, 31-88

GMODE (global mode entry), 31-40

GPLn (general-purpose signals), 11-76

GSMR (general SCC mode register)

AppleTalk mode, 26-4

HDLC bus protocol, programming, 22-22

overview, 20-3

GSMR_H,, 31-96, 31-98, 31-99

gsmr_h,, 31-96, 31-98, 31-99

HDLC mode

accessing the bus, 22-18

bus controller, 22-16

collision detection, 22-16, 22-19

commands, 22-5

delayed RTS mode, 22-20

error handling, 22-5

fast communications controllers (FCCs)

bit stuffing, 37-1

error control, 37-1

error handling, 37-6

FCCE, 37-14

FCCM, 37-14

FCCS, 37-16

features list, 37-1

FPSMR, 37-7

frame reception, 37-3

frame transmission, 37-2

overview, 37-1

parameter RAM, 37-3

programming model, 37-5

receive commands, 37-6

reception errors, 37-6

RxBD, 37-9

transmission errors, 37-6

transmit commands, 37-5

TxBD, 37-12

features list, 22-1

GSMR, HDLC bus protocol programming, 22-22

multi-master bus configuration, 22-17

overview, 22-1

parameter RAM, 22-3

performance, increasing, 22-19

programming example, 22-14, 22-22

programming the controller, 22-4

PSMR, 22-7

RxBD, 22-8

single-master bus configuration, 22-18

TxBD, 22-11

using the TSA, 22-21

HID0 register

bit settings, 2-11

doze, nap, sleep, DPM bits, 2-12

I2ADD (I

2C address) register, 40-6

I2BRG (I

2C baud rate generator) register, 40-7

2C controller

block diagram, 40-1

BRGCLK, 40-2

clocking and pin functions, 40-2

commands, 40-11

features list, 40-2

loopback testing, 40-4

master read (slave write), 40-4

master write (slave read), 40-3

multi-master considerations, 40-5

parameter RAM, 40-9

programming model, 40-5

registers, 40-5

RxBD, 40-12

slave read (master write), 40-3

slave write (master read), 40-4

transfers, 40-2

TxBD, 40-13

I2C memory map,, 3-18

I2CER (I

2C event register), 40-7

I2CMR (I

2C mask register), 40-7

I2COM (I

2C command) register, 40-8

I2MOD (I

2C mode) register, 40-6

IDL interface programming,, 15-29

IDL interface support, 15-25

IDMA emulation

auto buffer, 19-15

buffer chaining, 19-15

buffers, 19-23

bus exceptions, 19-27

commands, 19-26

controlling 60x bus bandwidth, 19-11

DACKx, 19-13

DCM, 19-18

DONEx, 19-14

DREQx, 19-13

DTS/STS programming, 19-21

dual-address transfers, 19-10

edge-sensitive mode, 19-14

exception, bus, 19-27

external request mode, 19-8

features list, 19-5

IDMR, 19-23

IDSR, 19-23

level-sensitive mode, 19-14

MPC8280 Datasheet(PDF) 1365 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1365 Page - Freescale Semiconductor, Inc

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