MPC8280 datasheet(1366/1386 Pages) FREESCALE

1366 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Index-12

Freescale Semiconductor

normal mode, 19-9

operand transfers, recognizing, 19-28

operation, 19-15

overview, 19-5

parallel I/O register programming, 19-28

parameter RAM, 19-16

priorities, 19-12

programming examples, 19-29

programming the parallel I/O registers, 19-28

signals, 19-13

single address transfers (fly-by), 19-10

transfers, 19-6

IDMA parameter RAM,, 19-16

IDMR (IDMA mask registers), 19-23

IDSR (IDMA event (status) register), 19-23

IEEE 1149.1 test access port

block diagram, 1-2

boundary scan register, 1-3

instruction decoding, 1-6

instruction register, 1-5

nonscan chain operation, 1-7

overview, 1-1

restrictions, 1-7

TAP controller, 1-2

IMA, 34-1

FCC programming

registers, 34-26

features, 34-1

ATM features not supported, 34-4

impact on MPC8280 features, 34-4

MPC8280 versions supported, 34-3

PHY-layer devices supported, 34-3

references, 34-3

versions supported, 34-3

microcode architecture, 34-10

function partitioning, 34-10

plane management functions, 34-11

receive, 34-17

cell processing activation function, 34-22

cell processing task, 34-24

cell reception task, 34-17

IDCR-regulated cell processing, 34-23

on-demand cell processing, 34-22

summary, 34-21

transmit, 34-11

non-TRL operation, 34-13

transmit queue (ITC mode), 34-14

TRL operation, 34-12

user plan functions, 34-11

programming model, 34-25

APC programming, 34-56

ABR, 34-57

CBR, UBR, VBR, and UBR+, 34-57

data structure organization, 34-25

exceptions, 34-49

ICP cell reception exceptions, 34-51

interrupt queue entry, 34-50

FCC programming

IMA-specific parameters, 34-26

parameters, 34-26

GMODE, 34-26

RCELL_TMP_BASE, 34-26

TCELL_TMP_BASE, 34-26

group tables, 34-30

group receive control (IGRCNTL), 34-38

group receive state (IGRSTATE), 34-39

group receive table entry, 34-36

group transmit state (IGTSTATE), 34-32

ICP cell templates, 34-33

receive group frame size, 34-39

receive group order tables, 34-40

transmit group order table, 34-32

transmit table entry, 34-30

group transmit control (IGTCNTL), 34-31

IDCR timer programming, 34-52

FCC parameter shadow, 34-52

on-the-fly FCC parameter changes, 34-53

programming, 34-53

unavailable MPC8280 features, 34-52

IDCR counter algorithm, 34-55

IDCR events, 34-55

IDCR root parameters, 34-54

IDCR table entry, 34-54

IDCR_Init command, 34-54

master clock, 34-52

IMA FCC programming, 34-26

link tables, 34-41

link receive statistics table, 34-48

link receive table entry, 34-44

link receive control (ILRCNTL), 34-46

link receive state (ILRSTATE), 34-47

link transmit table entry, 34-41

ILTCNTL, 34-42

link transmit state (ILTSTATE), 34-43

transmit interrupt status (ITINTSTAT), 34-43

root table, 34-27

control (IMACNTL), 34-29

structures in external memory, 34-48

transmit queues, 34-48

delay compression buffers (DCB), 34-49

protocol overview, 34-4

IMA cells, 34-7

control cells, 34-7

filler cells, 34-10

MPC8280 Datasheet(PDF) 1366 Page - Freescale Semiconductor, Inc

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