MPC8280 datasheet(1368/1386 Pages) FREESCALE

1368 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Index-14

Freescale Semiconductor

EDO interface connection, MPC8280 to 60x bus, 11-92

error checking and correction (ECC), 11-8

external master support, 11-102

external support, 11-10

features common to all machines, 11-5

features list, 11-3

general-purpose chip-select machine (GPCM)

access termination, external, 11-61

assertion timing, 11-53

common features, 11-5

differences between MPC8xx and MPC8280, 11-63

external access termination, 11-61

implementation differences with UPMs and SDRAM

machine, 11-6

interface signals, 11-52

MPC8xx versus MPC8280, 11-63

OE timing, 11-58

overview, 11-51

programmable wait state configuration, 11-58

PSDVAL, 11-58

read access extended hold time, 11-59

relaxed timing, 11-56

SRAM configuration, 11-52

strobe signal behavior, 11-53

terminating external accesses, 11-61

timing configuration, 11-53

write enable deassertion timing, 11-54

GPLn timing example, 11-69

implementation differences between machines, 11-6

machine selection, 11-5

MAR in 60x-compatible mode, 11-77

new features supported, 11-1

overview, 11-1

page hit checking, 11-7

parity byte select (PBSE), 11-10

parity checking, 11-8

parity generation, 11-8

programming model, 11-12

PSDVAL, 11-10, 11-58

SDRAM machine (synchronous DRAM machine)

address multiplexing, 11-37

bank interleaving, 11-36

BSMA bit, 11-37

commands, JEDEC-standard, 11-35

common features, 11-5

configuration example, 11-48

implementation differences with UPMs and GPCM, 11-6

JEDEC-standard commands, 11-35

MODE-SET command timing, 11-47

overview, 11-33

page mode support, 11-36

parameters

activate-to-read/write interval, 11-39

column address to first data out, 11-40

last data in to precharge, 11-41

last data out to precharge, 11-41

overview, 11-38

precharge-to-activate interval, 11-39

refresh recovery interval (RFRC), 11-42

pipeline accesses, 11-36

power-on initialization, 11-35

read/write transactions supported, 11-46

refresh, 11-47

SDAM bit, 11-37

supported configurations, 11-35

TEA generation, 11-8

UPMs (user-programmable machines)

access times, handling devices, 11-102

address control bits, 11-77

address multiplexing, 11-77

clock timing, 11-67

common features, 11-5

data sample control, 11-77

data valid, 11-77

differences between MPC8xx and MPC8280, 11-80

DRAM configuration example, 11-79

EDO interface example, 11-92

exception requests, 11-67

hierarchical bus interface example, 11-102

implementation differences with SDRAM machine and

GPCM, 11-6

loop control, 11-76

memory access requests, 11-66

memory system interface example, 11-81

MPC8xx versus MPC8280, 11-80

overview, 11-63

programming the UPM, 11-67

RAM array, 11-69

RAM word, 11-70

refresh timer requests, 11-66

requests, 11-65

signal negation, 11-78

signals, 11-63

software requests, 11-67

UPWAIT signal, 11-78

wait mechanism, 11-78

Memory management units (MMUs), 2-8

memory map

BRGs,, 3-18

clocks and reset keys,, 3-5

PIP,, 3-13

Memory maps

MPC8280 Datasheet(PDF) 1368 Page - Freescale Semiconductor, Inc

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