MPC8280 datasheet(1369/1386 Pages) FREESCALE

1369 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Index-15

cross-reference guide, 3-1

quick reference guide, 3-1

serial communications controllers (SCCs)

HDLC mode, 22-3

serial management controllers (SMCs)

GCI mode, 28-31

transparent mode, 28-6

UART mode, 28-6

Microcode revision number, 14-12

Modes

60x bus mode

60x-compatible bus mode, 8-3

address latch enable (ALE), 11-10

data streaming mode, 8-25

extended transfer mode, 8-18

no-pipeline mode, 8-23

one-level pipeline mode, 8-23

single-MPC8280 bus mode, 8-2

ATM controller

APC modes, 31-8

external rate mode, 31-6

internal rate mode, 31-6

transmit rate modes, 31-6

BISYNC mode, 23-1

cascaded mode, 18-3

echo mode, 28-1

HDLC mode, 22-1

hunt mode, 21-9

IDMA emulation

edge-sensitive mode, 19-14

external request mode, 19-8

level-sensitive mode, 19-14

normal mode, 19-9

loopback mode, 28-1

NMSI mode, synchronization, 24-3

SCC AppleTalk mode, 26-1

serial interface (SI)

echo mode, 15-7

serial peripheral interace (SPI)

master mode, 39-3

slow go, 18-2

transparent mode

overview, 38-1

serial communications controllers (SCCs), 24-1

serial management controllers (SMCs), 28-20

UART mode

serial communications controllers (SCCs), 21-1

serial management controllers (SMCs), 28-10

MPTPR (memory refresh timer prescaler register), 11-32

Multi-channel controllers (MCCs)

CHAMR

HDLC mode, 29-8

transparent mode, 29-13, 29-15

channel extra parameters, 29-28

commands, 29-34

data structure organization, 29-2

exceptions, 29-35

features list, 29-1

global parameters, 29-4, 29-15

HDLC parameters (channel-specific), 29-5

initialization, 29-47

INTMSK, 29-15

MCCE, 29-37

MCCFx, 29-33

MCCM, 29-37

parameters for transparent operation, 29-11

RSTATE, 29-10

RxBD, 29-42

TSTATE, 29-7

TxBD, 29-45

MxMR (machine x mode registers), 11-26

NMSI (non-multiplexed serial interface)

configuration, 16-4

SMC NMSI connection, receive and transmit, 28-2

synchronization in NMSI mode, transparent operation,

24-3

Operations

atomic bus operation, 11-9

digital phase-locked loop (DPLL) operation, 20-21

SMC buffer descriptor, 28-4

transparent operation, NMSI sychronization, 24-3

ORx (option registers), 11-15

Parallel I/O ports

block diagram, 41-6

features, 41-1

overview, 41-1

PDATx, 41-2

PDIRx, 41-3

pin assignments (port A–port D), 41-8–41-20

PODRx, 41-1

port C interrupts, 41-20

port pin functions, 41-6

PPAR, 41-4

programming options, 41-8

PSORx, 41-4

registers, 41-1

MPC8280 Datasheet(PDF) 1369 Page - Freescale Semiconductor, Inc

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