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MPC8280 Datasheet(PDF) 1370 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 1370 Page - Freescale Semiconductor, Inc |
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1370 / 1386 page ![]() MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-16 Freescale Semiconductor Parameter RAM ATM controller, 31-36 fast communications controllers (FCCs) Fast Ethernet mode, 36-8 HDLC mode, 37-3 overview, 30-12 HDLC mode, 22-3 I 2C controller, 40-9 IDMA emulation, 19-16 memory map, 27-12 serial communications controllers (SCCs) base addresses, 20-14 BISYNC mode, 23-3 overview, 20-13 UART mode, 21-3 serial management controllers (SMCs) GCI mode, 28-31 overview, 28-5, 28-30 transparent mode, 28-6 UART mode, 28-6 serial peripheral interface (SPI), 39-10 USB controller, 27-12 parameter RAM,, 14-25 Parity byte select (PBSE), 11-10 PCI bridge, 9-1 60x bus arbitration priority, 9-4 60x bus masters, 9-4 address map, 9-21 address decode flow chart, 9-21, 9-22, 9-23 address translation, 9-24 PCI inbound, 9-25 PCI outbound, 9-26 example, 9-24 programming, 9-24 SIU registers, 9-26 arbitration example, 9-20 burst read example, 9-10 burst write example, 9-11 clocking, 9-3 compact PCI hot swap specification support, 9-4 CompactPCI Hot Swap specification support, 9-5 configuration registers, 9-27 memory-mapped configuration registers, 9-27 discard timer control register (PTCR), 9-32 error address capture register (PCI_EACR), 9-39 error control capture register (PCI_ECCR), 9-40 error control register (ECR), 9-38 error data capture register (PCI_EDCR), 9-40 error mask register (EMR), 9-37 error status register (ESR), 9-35 general purpose control register (GPCR), 9-33 inbound base address registers (PIBARx), 9-42 inbound comparison mask registers (PICMRx), 9-43 inbound translation address registers (PITARx), 9-42 message unit (I2O) registers, 9-30 PCI general control register (PCI_GCR), 9-35 PCI outbound base address registers (POBARx), 9-31 PCI outbound comparison mask registers (POCMRx), 9-31 PCI outbound translation address registers (POTARx), 9-30 PCI bridge, 9-45 BIST control register, 9-53 device ID register, 9-47 general purpose local access base address registers (GPLABARx), 9-54 Hot Swap control status register, 9-61 initializing the PCI configuration registers, 9-64 PCI bus arbiter configuration register, 9-60 PCI bus base class code register, 9-51 PCI bus cache line size register, 9-51 PCI bus capabilities pointer register, 9-56 PCI bus command register, 9-47 PCI bus function register, 9-59 PCI bus internal memory-mapped registers base address register (PIMMRBAR), 9-53 PCI bus interrupt line register, 9-57 PCI bus interrupt pin register, 9-57 PCI bus latency timer register, 9-52 PCI bus MAX LAT, 9-58 PCI bus MIN GNT, 9-58 PCI bus programming interface register, 9-50 PCI bus status register, 9-48 PCI configuration register access from core, 9-62 PCI configuration register access in Big-Endian mode, 9-62, 9-63 PCI Hot Swap register block, 9-61 reader type register, 9-53 revision ID register, 9-49 subclass code register, 9-51 subsystem device ID register, 9-56 subsystem vendor ID register, 9-55 vendor ID register, 9-46 DMA controller, 9-85 block diagram, 9-85 descriptors, 9-95 Big Endian mode, 9-96 Little Endian mode, 9-97 operation, 9-85 byte count registers (DMABCRx), 9-93 current descriptor address registers (DMACDARx), 9-91 destination address registers (DMADARx), 9-93 direct mode, 9-86 |
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