TMPR4956C datasheet(9/286 Pages) TOSHIBA

9 / 286 page

Table of Contents

11.3.13 Data Rate Control...............................................................................................................11-55

11.3.14 Consecutive SysAD Bus Transactions.................................................................................. 11-56

11.3.15 Starvation and Deadlock Avoidance .................................................................................... 11-58

11.3.16 Discarding and Re-Executing Read Command .................................................................... 11-58

11.3.17 Multiple Drivers on the SysAD Bus ..................................................................................... 11-59

11.3.18 Signal Codes ....................................................................................................................... 11-60

11.3.19 Physical Addresses ..............................................................................................................11-62

11.3.20 Mode Register of System Interface (G2SConfig).................................................................. 11-62

11.3.21 Read Time Out Counter (MODE43* = 0) ........................................................................... 11-63

12.

TX4956 Processor Interrupts ........................................................................................................... 12-1

12.1 Nonmaskable Interrupt................................................................................................................ 12-2

12.2 External Interrupts....................................................................................................................... 12-2

12.3 Interrupts by External Write Through SysAD[6:0] ....................................................................... 12-2

12.4 Software Interrupt........................................................................................................................ 12-2

12.5 Timer Interrupt............................................................................................................................ 12-3

12.6 Masking of the TX4956 Interrupts............................................................................................... 12-3

12.7 Recognition of the Processor Interrupts ....................................................................................... 12-3

13.

Power-Saving Modes ....................................................................................................................... 13-1

13.1 Halt Mode ................................................................................................................................... 13-1

13.2 Doze Mode.................................................................................................................................. 13-1

13.3 Status Shifts ................................................................................................................................. 13-2

14.

JTAG Interface................................................................................................................................ 14-1

14.1 What Boundary Scanning Is ........................................................................................................ 14-1

14.2 Signal Summary .......................................................................................................................... 14-2

14.3 JTAG Controller and Registers .................................................................................................... 14-3

14.3.1

Instruction Register ............................................................................................................... 14-3

14.3.2

Bypass Register ..................................................................................................................... 14-4

14.3.3

Boundary-Scan Register(BSR) ............................................................................................... 14-5

14.3.4

Device Identification Register................................................................................................ 14-6

14.3.5

Test Access Port (TAP)..........................................................................................................14-7

14.3.6

TAP Controller ..................................................................................................................... 14-7

14.3.7

Controller Reset .................................................................................................................... 14-7

14.3.8

TAP Controller ..................................................................................................................... 14-8

14.4 Instructions for JTAG................................................................................................................ 14-12

14.4.1

The EXTEST Instruction .................................................................................................... 14-12

14.4.2

The SAMPLE/PRELOAD Instruction ............................................................................... 14-13

14.4.3

The BYPASS Instruction..................................................................................................... 14-14

14.4.4

The IDCODE Instruction ................................................................................................... 14-14

15.

CPU Instruction Set Summary ........................................................................................................ 15-1

15.1 Introduction................................................................................................................................. 15-1

15.2 Instruction Format....................................................................................................................... 15-1

15.3 Instruction Set Overview.............................................................................................................. 15-2

15.3.1

Load and Store Instructions (Table 15.3.1) ............................................................................ 15-2

15.3.2

Computational Instructions (Table 15.3.2)............................................................................. 15-3

15.3.3

Jump and Branch Instructions (Table 15.3.3)......................................................................... 15-4

15.3.4

Special Instructions (Table 15.3.4) ......................................................................................... 15-5

15.3.5

Exception Instructions (Table 15.3.5)..................................................................................... 15-5

15.3.6

Coprocessor Instructions (Table 15.3.6) ................................................................................. 15-6

15.3.7

CP0 Instructions (Table 15.3.7) ............................................................................................. 15-6

15.3.8

Multiply and Divide Instructions (Table 15.3.8)..................................................................... 15-7

15.3.9

Debug Instructions (Table 15.3.9).......................................................................................... 15-7

15.3.10 Other Instructions (Table 15.3.10) ......................................................................................... 15-7

15.4 Instruction Execution Cycles........................................................................................................ 15-7

15.5 Defining Access Types................................................................................................................. 15-8

15.6 Bit Encoding of CPU Instruction OPcodes .................................................................................. 15-9

16.

FPU Instruction Set Details............................................................................................................. 16-1

16.1 Instruction Formats ..................................................................................................................... 16-1

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