S29GL01GS10DFIV13 datasheet(68/108 Pages) CYPRESS

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Document Number: 001-98285 Rev. *R

Page 68 of 108

S29GL01GS/S29GL512S

S29GL256S/S29GL128S

9.4.3

Page Read

After a Random Read access is completed, if CE# remains Low, OE# remains Low, the AMAX to A4 address signals remain stable,

and any of the A3 to A0 address signals change, a new access within the same Page begins. The Page Read completes much

faster (tPACC) than a Random Read access.

9.5

Write

9.5.1

Asynchronous Write

When WE# goes Low after CE is Low, there is a transition from one of the read states to the Write state. If WE# is Low before CE#

goes Low, there is a transition from the Standby state directly to the Write state without beginning a read access.

When CE# is Low, OE# is High, and WE# goes Low, a write data transfer begins. Note, OE# and WE# should never be Low at the

same time to ensure no data bus contention between the host system and memory. When the asynchronous write cycle timing

requirements are met the WE# can go High to capture the address and data values in to EAC command memory.

Address is captured by the falling edge of WE# or CE#, whichever occurs later. Data is captured by the rising edge of WE# or CE#,

whichever occurs earlier.

When CE# is Low before WE# goes Low and stays Low after WE# goes High, the access is called a WE# controlled Write. When

WE# is High and CE# goes High, there is a transition to the Standby state. If CE# remains Low and WE# goes High, there is a

transition to the Read with Output Disable state.

When WE# is Low before CE# goes Low and remains Low after CE# goes High, the access is called a CE# controlled Write. A CE#

controlled Write transitions to the Standby state.

If WE# is Low before CE# goes Low, the write transfer is started by CE# going Low. If WE# is Low after CE# goes High, the address

and data are captured by the rising edge of CE#. These cases are referred to as CE# controlled write state transitions.

Write followed by Read accesses, in which CE# remains Low between accesses, requires an address change to initiate the

following read access.

Back to Back accesses, in which CE# remains Low between accesses, requires an address change to initiate the second access.

The EAC command memory array is not readable by the host system and has no ASO. The EAC examines the address and data in

each write transfer to determine if the write is part of a legal command sequence. When a legal command sequence is complete the

EAC will initiate the appropriate EA.

9.5.2

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on WE# will not initiate a write cycle.

9.5.3

Logical Inhibit

Write cycles are inhibited by holding OE# at VIL, or CE# at VIH, or WE# at VIH. To initiate a write cycle, CE# and WE# must be Low

(VIL) while OE# is High (VIH).

S29GL01GS10DFIV13 Datasheet(PDF) 68 Page - Cypress Semiconductor