ADS54J40 datasheet(26/88 Pages) TI2

26 / 88 page

BPF

LPF

Mode Selection Using

DECFIL MODE[3:0] Register Bits

cos(2 n Œ fmix / fS)

(1)

sin(2 n Œ fmix / fS)

(1)

Decimate-by-4, I-Data (At 250 MSPS)

Ch X

Interleaving

Engine,

Digital

Features

To JESD

Encoder

1.0 GSPS

Data, x(n)

LPF

Decimate-by-4 Q-Data (At 250 MSPS)

Default 12-Bit Data (At 1.0 GSPS)

Decimate-by-2 Data (At 500 MSPS)

Decimate-by-4 Data (At 250 MSPS)

Input Frequency (MHz)

200

400

600

800 1000 1200 1400 1600 1800 2000

-18

-15

-12

-9

-6

-3

D056

ADS54J20

SBAS766B – MAY 2016 – REVISED JANUARY 2017

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Product Folder Links: ADS54J20

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Feature Description (continued)

The input bandwidth shown in Figure 58 is measured with respect to a 50-Ω differential input termination at the

ADC input pins.

Figure 58. Transfer Function versus Frequency

8.3.2 DDC Block

The ADS54J20 has an optional digital down-converter (DDC) block that can be enabled via an SPI register write.

Each ADC channel is followed by a DDC block consisting of three different decimate-by-2 and decimate-by-4

finite impulse response (FIR) half-band filter options. The different decimation filter options can be selected via

SPI programming.

Figure 59 shows the signal processing done inside the DDC block of the ADS54J20.

(1)

In IQ decimate-by-4 mode, the mixer frequency is fixed at fmix = fS / 4. For fS = 1.0 GSPS and fmix = 250 MHz.

Figure 59. DDC Block

ADS54J40 Datasheet(PDF) 26 Page - Texas Instruments

ADS54J40 Datasheet(HTML) 26 Page - Texas Instruments

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