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ADS54J40 Datasheet(PDF) 39 Page - Texas Instruments |
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ADS54J40 Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 88 page ![]() 39 ADS54J20 www.ti.com SBAS766B – MAY 2016 – REVISED JANUARY 2017 Product Folder Links: ADS54J20 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated 8.4.2.2 JESD204B Test Patterns There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J20 supports a clock output, encoded, and a PRBS (215 – 1) pattern. These test patterns can be enabled via an SPI register write and are located in the JESD digital page of the JESD bank. 8.4.2.3 JESD204B Frame The JESD204B standard defines the following parameters: • L is the number of lanes per link. • M is the number of converters per device. • F is the number of octets per frame clock period, per lane. • S is the number of samples per frame per converter. 8.4.2.4 JESD204B Frame Table 10 lists the available JESD204B formats and valid ranges for the ADS54J20 when the decimation filter is not used. The ranges are limited by the SerDes lane rate and the maximum ADC sample frequency. NOTE The 16-bit data going to the JESD 8b, 10b encoder are formed by padding four 0s as LSBs into the 12-bit ADC data. Table 10. Default Interface Rates L M F S DECIMATION MINIMUM RATES MAXIMUM RATES SAMPLING RATE (MSPS) SERDES BIT RATE (Gbps) SAMPLING RATE (MSPS) SERDES BIT RATE (Gbps) 4 2 1 1 Not used 250 2.5 1000 10.0 4 2 4 4 Not used 250 2.5 1000 10.0 8 2 2 4 Not used 500 2.5 1000 5.0 (1) Blue shading indicates channel A and yellow shading indicates channel B. NOTE In the LMFS = 8224 row of Table 11, the sample order on the lanes is DA2, DA3, DA1, and DA0 for channel A. Similarly for channel B, the sample order on the lanes is DB2, DB3, DB1, and DB0. The detailed frame assembly is shown in Table 11. Table 11. Default Frame Assembly(1) OUTPUT LANE LMFS = 4211 LMFS = 4244 LMFS = 8224 DA0 A3[11:4] A3[3:0], 0000 DA1 A0[3:0], 0000 A2[11:4] A2[3:0], 0000 A3[11:4] A3[3:0], 0000 A2[11:4] A2[3:0], 0000 DA2 A0[11:4] A0[11:4] A0[3:0], 0000 A1[11:4] A1[3:0], 0000 A0[11:4] A0[3:0], 0000 DA3 A1[11:4] A1[3:0], 0000 DB0 B3[11:4] B3[3:0], 0000 DB1 B0[3:0], 0000 B2[11:4] B2[3:0], 0000 B3[11:4] B3[3:0], 0000 B2[11:4] B2[3:0], 0000 DB2 B0[11:4] B0[11:4] B0[3:0], 0000 B1[11:4] B1[3:0], 0000 B0[11:4] B0[3:0], 0000 DB3 B1[11:4] B1[3:0], 0000 |
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