SRC4392IPFBT datasheet(22/95 Pages) TI2

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SRC4392

SBFS029D – DECEMBER 2005 – REVISED DECEMBER 2012

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PRODUCT OVERVIEW

The SRC4392 is a two-channel asynchronous sample rate converter (SRC) with an integrated digital audio

interface receiver and transmitter (DIR and DIT). Two audio serial ports, Port A and Port B, support input and

output interfacing to external data converters, signal processors, and logic devices. On-chip routing logic

provides for flexible interconnection between the five functional blocks. The audio serial ports, DIT, and SRC may

be operated at sampling rates up to 216kHz. The DIR is specified for a PLL lock range that includes sampling

rates from 20kHz to 216kHz. All function blocks support audio data word lengths up to 24 bits.

The SRC4392 requires an external host processor or logic for configuration control. The SRC4392 includes a

user-selectable serial host interface, which operates as either a 4-wire serial peripheral interface (SPI) port or a

2-wire Philips I2C bus interface. The SPI port operates at bit rates up to 40MHz. The I2C bus interface may be

operated in standard or fast modes, supporting operation at 100kbps and 400kbps, respectively. The SPI and I2C

interfaces provide access to internal control and status registers, as well as the buffers utilized for the DIR and

DIT channel status and user data.

The asynchronous SRC is based upon the successful SRC4192 core from Texas Instruments. The SRC in the

SRC4392 has been further enhanced to provide exceptional jitter attenuation characteristics, helping to improve

overall application performance. The SRC operates over a wide input-to-output sampling ratio range, from 1:16

to 16:1 continuous. The input-to-output sampling ratio is determined automatically by the SRC rate estimation

circuitry, with the digital re-sampler parameters being updated in real-time without the need for programming.

Interpolation and decimation filter delay are user-selectable. Additional SRC features include de-emphasis

filtering, output word length reduction, output attenuation and muting, and input-to-output sampling ratio readback

via status registers.

The digital interface receiver (DIR) includes four differential input line receiver circuits, suitable for balanced or

unbalanced cable interfaces. Interfacing to optical receiver modules and CMOS logic devices is also supported.

The outputs of the line receivers are connected to a 1-of-4 data selector, referred to as the receiver input

multiplexer, which is utilized to select one of the four line receiver outputs for processing by the DIR core. The

outputs of the line receivers are also connected to a second data selector, the bypass multiplexer, which may be

used to route input data streams to the DIT CMOS output buffer and differential line driver functions. This

configuration provides a bypass signal path for AES3-encoded input data streams.

The DIR core decodes the selected input stream data and separates the audio, channel status, user, validity, and

parity data. Channel status and user data is stored in block-sized buffers, which may be accessed via the SPI or

I2C serial host interface, or routed directly to the general-purpose output pins (GPO1 through GPO4). The validity

and parity bits are processed to determine error status. The DIR core recovers a low jitter master clock, which

may be utilized to generate word and bit clocks using on-chip or external logic circuitry.

The digital interface transmitter (DIT) encodes digital audio input data into an AES3-formatted output data

stream. Two DIT outputs are provided, including a differential line driver and a CMOS output buffer. Both the line

driver and buffer include 1-of-2 input data selectors, which are utilized to choose either the output of the DIT

AES3 encoder, or the output of the bypass multiplexer. The line driver output is suitable for balanced or

unbalanced cable interfaces, while the CMOS output buffer supports interfacing to optical transmitter modules

and external logic or line drivers. The DIT includes block-sized data buffers for both channel status and user

data. These buffers are accessed via either the SPI or I2C host interface, or may be loaded directly from the DIR

channel status and user data buffers.

The SRC4392 includes four general-purpose digital outputs, or GPO pins. The GPO pins may be configured as

simple logic outputs, which may be programmed to either a low or high state. Alternatively, the GPO pins may be

connected to one of 14 internal logic nodes, allowing them to serve as functional, status, or interrupt outputs. The

GPO pins provide added utility in applications where hardware access to selected internal logic signals may be

necessary.

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