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SRC4392IPFBT Datasheet(PDF) 30 Page - Texas Instruments |
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SRC4392IPFBT Datasheet(HTML) 30 Page - Texas Instruments |
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30 / 95 page  PL 1 L AE 3 S Decoder Pulse Generator PL 2 L 128f S 256f S 512f S Clock Divider Divide by 1,2, 4,or8 DataStream De-M x u RX1+(pin1) RX1 (pin2) - RX2+(pin3) RX2 (pin4) - RX3+(pin5) RX3 (pin6) - RX4+(pin7) RX4 (pin8) - LOCK (pin 11) RXCKO (pin 12) RXCKO BYPMUX[10 : ] R MUX[ X 1:0] RXCLK MC K L RXCKI RXCKOF[1:0] Ch1 . (Left) Audio Ch2 . (Right) Audio Cha ne n l Status Channel Status User Daa t User Daa t UserAccess (UA)Buffers Receiver Access (RA)Buffers To DIT ToSPI orI CHostInterface 2 Receiver Sy c n Generator RCV_SYNC Errorand StatusOutputs ToDIT Buffer andLine Driver Reference Clock Source To DIT SY C N BLS (input) BLS (output) Block Start (Frame 0startshere) SRC4392 SBFS029D – DECEMBER 2005 – REVISED DECEMBER 2012 www.ti.com Figure 66. DIT Block Start Timing DIGITAL INTERFACE RECEIVER (DIR) OPERATION The DIR performs AES3 decoding and clock recovery and provides the differential line receiver functions. The lock range of the DIR includes frame/sampling rates from 20kHz to 216kHz. Figure 67 shows the functional block diagram for the DIR. Four differential line receivers are utilized for signal conditioning the encoded input data streams. The receivers can be externally configured for either balanced or unbalanced cable interfaces, as well as interfacing with CMOS logic level inputs from optical receivers or external logic circuitry. See Figure 68 for a simplified schematic for the line receiver. External connections are discussed in the Receiver Input Interfacing section. Figure 67. Digital Interface Receiver (DIR) Functional Block Diagram 30 Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated Product Folder Links: SRC4392 |
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