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SRC4392IPFBT Datasheet(PDF) 48 Page - Texas Instruments |
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SRC4392IPFBT Datasheet(HTML) 48 Page - Texas Instruments |
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48 / 95 page ![]() SRC4392 SBFS029D – DECEMBER 2005 – REVISED DECEMBER 2012 www.ti.com REGISTER AND DATA BUFFER ORGANIZATION The SRC4392 organizes the on-chip registers and data buffers into four pages. The currently active page is chosen by programming the Page Selection Register to the desired page number. The Page Selection Register is available on every register page at address 0x7F, allowing easy movement between pages. Table 2 indicates the page selection corresponding to the Page Selection Register value. Table 2. Register Page Selection Page Selection Register Value (Hex) Selected Register Page 00 Page 0, Control and Status Registers 01 Page 1, DIR Channel Status and User Data Buffers 02 Page 2, DIT Channel Status and User Data Buffers 03 Page 3, Reserved Register Page 0 contains the control registers utilized to configure the various function blocks within the SRC4392. In addition, status registers are provided for flag and error conditions, with many of the status bits capable of generating an interrupt signal when enabled. See Table 3 for the control and status register map. Register Page 1 contains the digital interface receiver (or DIR) channel status and user data buffers. These buffers correspond to the data contained in the C and U bits of the previously received block of the AES3- encoded data stream. The contents of these buffers may be read through the SPI or I2C serial host interface and processed as needed by the host system. See Table 5 for the DIR channel status buffer map, and Table 6 for the DIR user data buffer map. Register Page 2 contains the digital interface transmitter (or DIT) channel status and user data buffers. These buffers correspond to the data contained in the C and U bits of the transmitted AES3-encoded data stream. The contents of these buffers may be written through the SPI or I2C serial host interface to configure the C and U bits of the transmitted AES3 data stream. The buffers may also be read for verification by the host system. See Table 7 for the DIT channel status buffer map, and Table 8 for the DIT user data buffer map. Register Page 3 is reserved for factory test and verification purposes, and cannot be accessed without an unlock code. The unlock code remains private; the test modes disable normal operation of the device, and are not useful in customer applications. CONTROL REGISTERS See Table 3 for the control and status register map of the SRC4392. Register addresses 0x00 and 0x34 through 0x7E are reserved for factory or future use. All register addresses are expressed as hexadecimal numbers. The following pages provide detailed descriptions for each control and status register. 48 Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated Product Folder Links: SRC4392 |
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