STM32WBA62CGF6 datasheet(44/185 Pages) STMICROELECTRONICS

44 / 185 page

Functional overview

STM32WBA6xxx

44/185

DS14736 Rev 1

The SYSCFG TrustZone security secures the following configuration:

•

FPU interrupt configuration

•

Robustness features

•

I/O compensation and memory erase status

Some of the SYSCFG configuration bits security is defined by the security of other

peripherals:

•

The FMP high-drive mode of some I/Os configuration is secure when the

corresponding GPIO is secure.

•

The booster for I/Os analog switches configuration is secure when the ADC4 is secure.

3.16

Peripheral interconnect matrix

Several peripherals have direct connections between them, enabling autonomous

communication between them, and saving CPU resources (and power consumption). In

addition, these hardware connections allow fast and predictable latency.

Depending on the peripherals, these interconnections can operate in Run, Sleep and Stop

modes.

3.17

General purpose direct memory access controller (GPDMA)

The general purpose direct memory access (GPDMA) controller is a bus master and system

peripheral.

The GPDMA is used to perform programmable data transfers between memory-mapped

peripherals and/or memories via linked-lists, upon the control of an off-loaded CPU.

The GPDMA main features are:

•

Dual bidirectional AHB master

•

Memory-mapped data transfers from a source to a destination:

–

Peripheral-to-memory

–

Memory-to-peripheral

–

Memory-to-memory

–

Peripheral-to-peripheral

•

Autonomous data transfers during Run, Sleep and Stop 0 modes

•

Transfers arbitration based on a four-grade programmed priority at a channel level:

–

One high-priority traffic class, for time-sensitive channels (queue 3)

–

Three low-priority traffic classes, with a weighted round-robin allocation for

nontime-sensitive channels (queues 0, 1, 2)

•

Per channel event generation, on any of the following events: transfer complete or half

transfer complete or data transfer error or user setting error, and/or update linked-list

item error or completed suspension

•

Per channel interrupt generation, with separately programmed interrupt enable per

event

•

Eight concurrent DMA channels:

–

Per channel FIFO for queuing source and destination transfers

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