STM32WBA62CGF6 datasheet(23/185 Pages) STMICROELECTRONICS

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DS14736 Rev 1

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STM32WBA6xxx

Functional overview

3.7.1

TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either securable or

TrustZone-aware type as follows:

•

Securable: peripheral protected by an AHB/APB firewall gate that is controlled from

TZSC to define security properties

•

TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing

a specific TrustZone behavior such as a subset of registers being secure

3.7.2

Default TrustZone security state

The default system security state is detailed below:

•

CPU: Cortex-M33 is in secure state after reset. The boot address must be in secure

area.

•

Memory map: SAU is fully secure after reset, hence all memory map is fully secure.

Up to eight SAU configurable regions are available for security attribution.

•

Flash memory:

–

Flash memory security area is defined by watermark user options.

–

Flash memory block based area is nonsecure after reset.

•

SRAMs:

–

All are secure after reset, MPCBB is secure.

•

Peripherals:

–

Securable peripherals are nonsecure after reset.

–

TrustZone-aware peripherals are nonsecure after reset.

•

All GPIOs are secure after reset.

ICACHE Re-mappable

(Reserved)

0x1000 0000

0x17FF FFFF

Nonsecure

0x1800 0000

0x1FFF FFFF

SRAM

0x2000 0000

0x2FFF FFFF

Nonsecure

0x3000_0000

0x3FFF FFFF

Nonsecure callable

Secure or nonsecure callable

Peripherals

0x4000 0000

0x4FFF FFFF

Nonsecure

0x5000 0000

0x5FFF FFFF

Nonsecure callable

Secure or nonsecure callable

Reserved

0x6000 0000

0xDFFF FFFF

Nonsecure

Secure or nonsecure or nonsecure callable

Table 5. Example of memory map security attribution versus SAU configuration regions (contin-

Region description

Address range

IDAU security

attribution

SAU security

attribution typical

configuration

Final security

attribution

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