STM32WBA62CGF6 datasheet(53/185 Pages) STMICROELECTRONICS

53 / 185 page

DS14736 Rev 1

53/185

STM32WBA6xxx

Functional overview

The SAES peripheral is connected by hardware to the true random number generator RNG

(for side-channel resistance).

The SAES and AES peripherals support:

•

Compliant implementation of standard NIST Special Publication 197, Advanced

Encryption Standard (AES) and Special Publication 800-38A, Recommendation for

Block Cipher Modes of Operation

•

128-bit data block processing

•

Support for cipher keys length of 128- and 256-bit

•

Encryption and decryption with multiple chaining modes:

–

Electronic codebook (ECB) mode

–

Cipher block chaining (CBC) mode

–

Counter (CTR) mode

–

Galois counter mode (GCM)

–

Galois message authentication code (GMAC) mode

–

Counter with CBC-MAC (CCM) mode

•

528 or 743 clock cycle latency in ECB encryption mode for SAES processing one

128-bit block of data with, respectively, 128- or 256-bit key

•

51 or 75 clock cycle latency in ECB encryption mode for AES processing one 128-bit

block of data with, respectively, 128- or 256-bit key

•

Integrated round key scheduler to compute the last round key for AES ECB/CBC

decryption

•

256-bit register for storing the cryptographic key (four 32-bit registers), with key

atomicity enforcement

•

128-bit registers for storing initialization vectors (four 32-bit registers)

•

One 32-bit input buffer and one 32-bit output buffer

•

Automatic data flow control with support of single-transfer direct memory access (DMA)

using two channels (one for incoming data, one for processed data)

•

Data swapping logic to support 1-, 8-, 16- or 32-bit data

•

Possibility for software to suspend a message if the SAES/AES needs to process

another message with a higher priority (suspend/resume operation)

•

SAES additional features:

–

Security context enforcement for keys

–

Hardware secret key encryption/ decryption (wrapped key mode) and sharing with

faster AES peripheral (Shared key mode)

–

Protection against DPA (differential power analysis) and related side-channel

attacks

–

Optional hardware loading of two hardware secret keys (BHK, DHUK) that can be

XORed together

On top of standard AES encryption and decryption with a key loaded by software, SAES

peripheral makes possible the following advanced use cases:

•

Allow or deny the sharing of a key between a secure and a nonsecure application,

enforced by hardware

•

Encrypt once a key using side-channel resistant AES, then share it to a faster AES

engine by decrypting it (Shared key mode)

•

On-chip encrypted storage using secret DHUK

STM32WBA62CGF6 Datasheet(PDF) 53 Page - STMicroelectronics

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