STM32WBA62CGF6 datasheet(37/185 Pages) STMICROELECTRONICS

37 / 185 page

DS14736 Rev 1

37/185

STM32WBA6xxx

Functional overview

system clock is woken up and distributed to all peripherals enabled in the RCC. This

allows the DMA to access the enabled SRAM, and any enabled peripheral register (for

instance GPIO registers). When no peripheral requests its bus clock Stop 1 mode is

automatically re-entered when Stop 1 mode selected as low-power mode.

•

Automatic start of the peripheral thanks to hardware synchronous or asynchronous

triggers (such as I/Os edge detection and low-power timer event).

•

Wake-up from Stop mode with peripheral interrupt.

The GPDMA is fully functional and the linked-list is updated in Stop 0 mode, allowing the

different DMA transfers to be linked without any CPU wake-up. This can be used to chain

different peripherals transfers, or to write peripherals registers in order to change their

configuration while remaining in Stop 0 mode.

The DMA transfers from memory to memory can be started by hardware synchronous or

asynchronous triggers, and the DMA transfers between peripherals and memories can also

be gated by those triggers.

Here below some use-cases that can be done while remaining in Stop mode:

•

A/D conversion triggered by a low-power timer (or any other trigger)

–

wake-up from Stop mode on analog watchdog if the A/D conversion result is out of

programmed thresholds

–

wake-up from Stop mode on DMA buffer event

•

I2C slave reception or transmission, SPI reception, UART/LPUART reception

–

wake-up at the end of peripheral transfer or on DMA buffer event

•

I2C controller transfer, SPI transmission, UART/LPUART transmission, triggered by a

low-power timer (or any other trigger):

–

example: sensor periodic read

–

wake-up at the end of peripheral transfer or on DMA buffer event

•

Bridges between peripherals

–

example: ADC converted data transferred by communication peripherals

•

Data transfer from/to GPIO to/from SRAM for:

–

controlling external components

–

implementing data transmission and reception protocols

Table 10. Functionalities depending on the working mode(1)

Peripheral

Run

Sleep

Stop 0

Stop 1

Stop 2

Standby

retention

Standby

CPU

-R

Flash memory

O(2)

-R

Flash interface

-R

SRAM1

O(3)

-O(3)

SRAM2

O(3)

O(4) O(3)

O(3)

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