STM32WBA62CGF6 datasheet(54/185 Pages) STMICROELECTRONICS

54 / 185 page

Functional overview

STM32WBA6xxx

54/185

DS14736 Rev 1

•

Transport key generation by encrypting the device public unique ID with the application

secret BHK

•

Binding of device secure storage keys, using the secret derived hardware unique key

(DHUK) XORed with the secret boot hardware key (BHK). If BHK is lost, the whole

device secure storage is lost.

Note:

Encrypted storage or derived keys that are using DHUK or BHK, cannot be used anymore

when a security breach is detected.

3.26

HASH hardware accelerator (HASH)

The HASH is a fully compliant implementation of the secure hash algorithm

(SHA-1, SHA2-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and

the keyed-hash message authentication code (HMAC) algorithm. HMAC is suitable for

applications requiring message authentication.

The HASH computes Federal information processing standards (FIPS) approved digests of

length of 160, 224, 256 bits, for messages of up to (264 – 1) bits. It also computes 128 bits

digests for the MD5 algorithm.

The HASH main features are:

•

Suitable for data authentication applications, compliant with:

–

Federal Information Processing Standards Publication FIPS PUB 180-4, Secure

Hash Standard (SHA-1 and SHA-2 family)

–

Federal Information Processing Standards Publication FIPS PUB 186-4, Digital

Signature Standard (DSS)

–

Internet Engineering Task Force (IETF) Request For Comments RFC 1321, MD5

Message-Digest Algorithm

–

Internet Engineering Task Force (IETF) Request For Comments RFC 2104,

HMAC: Keyed-Hashing for Message Authentication and Federal Information

Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message

Authentication Code (HMAC)

•

Fast computation of SHA-1, SHA2-224, SHA-256, and MD5

–

82 (respectively 66) clock cycles for processing one 512-bit block of data using

SHA-1 (respectively SHA-256) algorithm

–

66 clock cycles for processing one 512-bit block of data using MD5 algorithm

Table 16. AES/SAES features

AES/SAES modes/features(1)

1. X = supported.

AES

SAES

ECB, CBC chaining

CTR, CCM, GCM chaining

AES 128-bit ECB encryption in cycles

528

DHUK and BHK key selection

Side-channel attacks resistance

Shared key between SAES and AES

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