STM32WBA62CGF6 datasheet(34/185 Pages) STMICROELECTRONICS

34 / 185 page

Stop 2(14)

LPR

OFF

ON(5)

LSE

LSI

BOR, PVD, RTC, TAMP, IWDG, SLEEP_TIMER,

LPUART1,

SPI3,

I2C3,

LPTIM1,

GPIO

All other peripherals are powered off.

Reset pin, all I/Os,

BOR, PVD, RTC, TAMP, IWDG, SLEEP_TIMER,

LPUART1,

SPI3,

I2C3,

LPTIM1

Standby

retention

LPR

OFF

ON(5)

LSE

LSI

BOR, RTC, TAMP, IWDG, SLEEP_TIMER

All other peripherals are powered off.

I/O configuration can be retained, floating, pull-

up or pull-down.

Reset pin, WKUPx (x = 1...8),

BOR, RTC, TAMP, IWDG, SLEEP_TIMER

Standby

OFF

All from mode Standby retention, except SLEEP_TIMER

1. LPR means that the main regulator is OFF and the low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. The flash memory can be put in power-down and its clock can be gated off when executing from SRAM.

4. The SRAM1 and SRAM2 clocks can be gated on or off independently.

5. The SRAM can be individually powered off to save power consumption.

6. HSI16 can be temporary enabled upon peripheral request, for autonomous functions with DMA or wake-up from Stop event detections.

7. The ADC conversion is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on conversion events.

8. UART and LPUART transmission and reception is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on transfer events.

9. SPI transmission and reception is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on transfer events.

10. I2C transmission and reception is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on transfer events.

11. LPTIM is functional and autonomous with DMA in Stop 0 mode, and can generate a wake-up interrupt on all events.

12. GPDMA is functional and autonomous in Stop 0 mode, and can generate a wake-up interrupt on events.

13. Active peripherals ADC, COMP, USART, LPUART, SPI, I2C and LPTIM, can generate bus clock request and/or a wake-up interrupt on event.

14. Active peripherals LPUART1, SPI3, I2C3 and LPTIM1, can generate bus clock request and/or a wake-up interrupt on event.

Table 9. Operating modes overview (continued)

Mode

Regulator(1) CPU

Flash

memory

SRAM Clocks

DMA and peripherals(2)

Wake-up source

STM32WBA62CGF6 Datasheet(PDF) 34 Page - STMicroelectronics

STM32WBA62CGF6 Datasheet(HTML) 34 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL