6.42

9

7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Feb.20.20

NOTES:

1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.

2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.

3. tBDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has

no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

Waveform of Read Cycles(5)

tRC

R/

W

CE

ADDR

tAA

OE

UB, LB

2740 drw 07

(4)

tACE

(4)

tAOE

(4)

tABE

(4)

(1)

tLZ

tOH

(2)

tHZ

(3,4)

tBDD

DATAOUT

BUSYOUT

VALID DATA

(4)

CE

2740 drw 08

tPU

ICC

ISB

tPD

,