7024SSLASHL datasheet(18/23 Pages) RENESAS

18 / 23 page

6.42

7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Feb.20.20

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT7024 RAMs.

isnotused,addresslocationsFFEandFFFarenotusedasmailboxes,

butaspartoftherandomaccessmemory.RefertoTruthTableIIIforthe

interruptoperation.

Busy Logic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.

TheBUSY pincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally

to prevent the write from proceeding.

TheuseofBUSYlogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

and use any BUSY indication as an interrupt source to flag the event of

anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis

notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave

modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

TheBUSYoutputsontheIDT7024SRAMinmastermode,arepush-

pull type outputs and do not require pull up resistors to operate. If these

RAMs are being expanded in depth, then the BUSY indication for the

resulting array requires the use of an external AND gate.

Width Expansion with BUSY Logic

Master/Slave Arrays

WhenexpandinganIDT7024RAMarrayinwidthwhileusing BUSY

logic, one master part is used to decide which side of the RAM array will

receive a BUSY indication, and to output that indication. Any number of

slaves to be addressed in the same address range as the master, use

the BUSYsignal as a write inhibit signal. Thus on the IDT7024 RAM the

BUSY pin is an output if the part is used as a master (M/S pin = VIH), and

theBUSYpinisaninputifthepartusedasaslave(M/Spin=VIL)as shown

in Figure 3.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decisioncouldresultwithonemasterindicatingBUSYononesideofthe

arrayandanothermasterindicatingBUSYononeothersideofthearray.

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

The BUSYarbitration, on a master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite

pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables.Failure

toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland

corrupted data in the slave.

Semaphores

TheIDT7024isanextremelyfastDual-Port4Kx16CMOSStaticRAM

withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.

TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port

RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby

thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe

usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe

Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, and both ports are

completelyindependentofeachother.Thismeansthattheactivityonthe

left port in no way slows the access time of the right port. Both ports are

identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,

orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphorelocation.Semaphoresareprotectedagainstsuchambiguous

situationsandmaybeusedbythesystemprogramtoavoidanyconflicts

inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave

anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM

enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol

on-chip power down circuitry that permits the respective port to go into

standbymodewhennotselected.Thisistheconditionwhichisshownin

Truth Table I where CE and SEM = VIH.

SystemswhichcanbestusetheIDT7024containmultipleprocessors

or controllers and are typically very high-speed systems which are

softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom

aperformanceincreaseofferedbytheIDT7024'shardwaresemaphores,

whichprovidealockoutmechanismwithoutrequiringcomplexprogram-

ming.

Software handshaking between processors offers the maximum in

systemflexibilitybypermittingsharedresourcestobeallocatedinvarying

configurations.TheIDT7024doesnotuseitssemaphoreflagstocontrol

anyresourcesthroughhardware,thusallowingthesystemdesignertotal

flexibilityinsystemarchitecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speedsystems.

How the Semaphore Flags Work

Thesemaphorelogicisasetofeightlatcheswhichareindependent

oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,

fromoneporttotheothertoindicatethatasharedresourceisinuse.The

semaphores provide a hardware assist for a use assignment method

called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore

latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft

processorwantstousethisresource,itrequeststhetokenbysettingthe

latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading

2740 drw 19

MASTER

Dual Port

RAM

BUSY (L) BUSY (R)

MASTER

Dual Port

RAM

BUSY (L) BUSY (R)

SLAVE

Dual Port

RAM

BUSY (L) BUSY (R)

SLAVE

Dual Port

RAM

BUSY (L) BUSY (R)

BUSY (L)

BUSY (R)

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