6.42

17

7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Feb.20.20

Truth Table IV —

Address BUSY Arbitration

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7024 are

push pull, not open drain outputs. On slaves, the BUSY asserted input internally inhibits write.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSYR outputs are driving LOW regardless of actual logic level on the pin.

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024.

2. There are eight semaphore flags written to via I/O0 and read from all the I/O's. These eight semaphores are addressed by A0-A2.

3. CE = VIH, SEM = VIL, to access the Semaphores. Refer to the Semaphore Read/Write Control Truth Table.

Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)

Functional Description

TheIDT7024providestwoportswithseparatecontrol,addressand

I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation

inmemory.TheIDT7024hasanautomaticpowerdownfeaturecontrolled

by CE. The CE controls on-chip power down circuitry that permits the

respectiveporttogointoastandbymodewhennotselected(CE=VIH).

Whenaportisenabled,accesstotheentirememoryarrayispermitted.

Interrupts

Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox

or message center) is assigned to each port. The left port interrupt flag

(INTL) is asserted when the right port writes to memory location FFE

(HEX), whereawriteisdefinedastheCE=R/W=VILpertheTruthTable

III.TheleftportclearstheinterruptbyaccessaddresslocationFFEaccess

when CER = OER = VIL, R/W is a "don't care". Likewise, the right port

interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation

FFF(HEX)andtocleartheinterruptflag(INTR),therightportmustaccess

thememorylocationFFF. Themessage(16bits)atFFEorFFFisuser-

defined,sinceitisanaddressableSRAMlocation.Iftheinterruptfunction

Inputs

Outputs

Function

CEL

CER

A0L-A11L

A0R-A11R

BUSYL(1)

BUSYR(1)

X

X

NO MATCH

H

H

Normal

HX

MATCH

H

H

Normal

XH

MATCH

H

H

Normal

L

L

MATCH

(2)

(2)

Write Inhibit(3)

2740 tbl 17

Functions

D0 - D15 Left

D0 - D15 Right

Status

No Action

1

1

Semaphore free

Left Port Writes "0" to Semaphore

0

1

Left port has semaphore token

Right Port Writes "0" to Semaphore

0

1

No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore

1

0

Right port obtains semaphore token

Left Port Writes "0" to Semaphore

1

0

No change. Left port has no write access to semaphore

Right Port Writes "1" to Semaphore

0

1

Left port obtains semaphore token

Left Port Writes "1" to Semaphore

1

1

Semaphore free

Right Port Writes "0" to Semaphore

1

0

Right port has semaphore token

Right Port Writes "1" to Semaphore

1

1

Semaphore free

Left Port Writes "0" to Semaphore

0

1

Left port has semaphore token

Left Port Writes "1" to Semaphore

1

1

Semaphore free

2740 tbl 18