6.42

7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

16

Feb.20.20

Truth Table III — Interrupt Flag(1,4)

Waveform of Interrupt Timing(1)

NOTES:

1. Assumes BUSYL = BUSYR = VIH.

2. If BUSYL = VIL, then no change.

3. If BUSYR = VIL, then no change.

4. INTR and INTL must be initialized at power-up.

2740 drw 17

ADDR"A"

INTERRUPT SET ADDRESS

CE"A"

R/

W"A"

tAS

tWC

tWR

(3)

(4)

tINS

(3)

INT"B"

(2)

2740 drw 18

ADDR"B"

INTERRUPT CLEAR ADDRESS

CE"B"

OE"B"

tAS

tRC

(3)

tINR

(3)

INT"B"

(2)

Left Port

Right Port

Function

R/WL

CEL

OEL

A11L-A0L

INTL

R/WR

CER

OER

A11R-A0R

INTR

L

L

X

FFF

X

X

X

X

X

L(2)

Set Right INTR Flag

X

X

XXX

X

L

L

FFF

H(3)

Reset Right INTR Flag

XXX

X

L(3)

L

L

X

FFE

X

Set Left INTL Flag

X

L

L

FFE

H(2)

XX

X

X

X

Reset Left INTL Flag

2740 tbl 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. See Interrupt Truth Table III.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.