6.42

7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

14

Feb.20.20

2740 drw 13

tDW

tAPS

ADDR"A"

tWC

DATAOUT "B"

MATCH

tWP

R/

W"A"

DATAIN "A"

ADDR"B"

tDH

VALID

(1)

MATCH

BUSY"B"

tBDA

VALID

tBDD

tDDD

(3)

tWDD

tBAA

Timing Waveform of Write with Port-to-Port Read and BUSY(2,4,5)(M/S = VIH)

Timing Waveform of Write with BUSY

NOTES:

1. tWH must be met for both BUSY input (slave) and output (master).

2. BUSY is asserted on port "B" Blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB is only for the 'Slave' Version.

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).

2. CEL = CER = VIL.

3. OE = VIL for the reading port.

4. If M/S = VIL (slave) then BUSY is an input BUSY"A" = VIL and BUSY"B" = don't care, for this example.

5. All timing is the same for both left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

2740 drw 14

R/

W"A"

BUSY"B"

tWP

tWB

R/

W"B"

tWH

(1)

(2)

(3)

,