6.42

11

7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Feb.20.20

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)

Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)

NOTES:

1. R/W or CE or UB & LB = VIH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a UB or LB = VIL and a CE = VIL and a R/W = VIL for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH = VIL to the end-of-write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE, R/W, UB, or LB.

7.

This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV steady state with the Output Test Load

(Figure 2).

8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP for (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified tWP .

9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be

met for either condition.

R/

W

tWC

tHZ

tAW

tWR

tAS

tWP

DATAOUT

(2)

tWZ

tDW

tDH

tOW

OE

ADDRESS

DATAIN

(6)

(4)

(4)

(7)

UB or LB

2740 drw 09

(9)

CE or SEM

(9)

(7)

(3)

2740 drw 10

tWC

tAS

tWR

tDW

tDH

ADDRESS

DATAIN

R/

W

tAW

tEW

UB or LB

(3)

(2)

(6)

CE or SEM

(9)

(9)