MK50H28 datasheet(19/64 Pages) STMICROELECTRONICS

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BIT

NAME

DESCRIPTION

TXON

TRANSMITTER ON indicates that the transmit ring access is enabled. TXON is set as

the Start primitive is issued if the DTX bit is ”0” or afterward as DTX is cleared. TXON is

cleared upon recognition of DTX being set, by sending a Stop primitive in CSR1, or by a

Bus RESET. If TXON is clear, the host may modify the Transmit Descriptor Rings entries

regardless of the state of the OWNA bits. TXON is READ ONLY; writing to this bit has no

effect.

RXON

RECEIVER ON indicates that the receive ring access is enabled. RXON is set as the

Start primitive is issued if the DRX bit is ”0” or afterward as DRX is cleared. RXON is

cleared upon recognition of DRX being set, by sending a Stop primitive in CSR1, or by a

Bus RESET. RXON is READ ONLY; writing to this bit has no effect.

INEA

INTERRUPT ENABLE allows the INTR I/O pin to be driven low when the Interrupt Flag

is set. If INEA = 1 and INTR = 1 the INTR I/O pin will be low. If INEA = 0 the INTR I/O

pin will be high, regardless of the state of the Interrupt Flag (TINT, RINT, or PINT) or

whether the Interrupt Desciptor Ring has been updated. INEA is READ/WRITE set by

writing a ”1” into this bit and is cleared by writing a ”0” into this bit, by Bus RESET, or by

issuing a Stop primitive. INEA may not be set while in the STOPPED Phase.

INTR

INTERRUPT FLAG indicates that one or more of the following interrupt causing

conditions has occurred: MISS, MERR, RINT, TINT, PINT. If INEA = 1 and INTR = 1 the

INTR I/O pin will be low. INTR is READ ONLY, writing this bit has no effect. INTR is

cleared as the specific interrupting condition bits are cleared. INTR is also cleared by

Bus RESET or by issuing a Stop primitive.

MERR

MEMORY ERROR is set when the MK50H28 is the Bus Master and READY has not

been asserted within 256 SYSCLKs (25.6 usec @ 10MHz) after asserting the address on

the DAL lines. When a Memory Error is detected, the MK50H28 releases the bus,

the receiver and transmitter are turned off, and an interrupt is generated if INEA = 1.

MERR is READ/CLEAR ONLY and is set by the chip and cleared by writing a ”1” into the

bit. Writing a ”0” has no effect. It is cleared by Bus RESET or by issuing a Stop primitive.

MISS

MISSED frame is set when the receiving channel loses a frame because it is either not

ready or does not own a receive buffer indicating loss of data. The Memory Address for

which MISS occurred can be determined by issuing a Status Request primitive (see

section 4.3.3 Status Buffer for additional details). When MISS is set, an interrupt will be

generated if INEA = 1. MISS is READ/CLEAR ONLY and is set by MK50H28 and

cleared by writing a ”1” into the bit. Writing a ”0” has no effect. It is also cleared by Bus

RESET or by issuing a Stop primitive.

ROR

RECEIVER OVERRUN indicates that the Receiver FIFO was full when the receiver was

ready to input data to the Receiver FIFO. The frame being received is lost, but is

probably recoverable if an upper level protocol is used. When ROR is set, an interrupt is

generated if INEA=1. ROR is READ/CLEAR ONLY and is set by MK50H28 and

cleared by writing a ”1” into the bit. Writing a ”0” has no effect. It is also cleared by Bus

RESET or by issuing a Stop primitive.

TUR

TRANSMITTER UNDERRUN indicates that the MK50H28 has aborted a frame since

data was late from memory. This condition is reached when the transmitter and

transmitter FIFO both become empty while transmitting a frame. When TUR is set, an

interrupt is generated if INEA = 1. TUR is READ/CLEAR ONLY and is set by MK50H28

and cleared by writing a ”1” into the bit. Writing a ”0” has no effect. It is also cleared by

Bus RESET or by issuing a Stop primitive.

PINT

PRIMITIVE INTERRUPT is set after the chip updates the primitive register to issue a

provider primitive. When PINT is set, an interrupt is generated if INEA =1. PINT is

READ/CLEAR ONLY and is set by MK50H28 and cleared by writing a ”1” into the bit.

Writing a ”0” has no effect. It is also cleared by Bus RESET or by issuing a Stop primitive.

TINT

TRANSMITTER INTERRUPT is set after the chip updates an entry in the Transmit

Descriptor Ring. When TINT is set, an interrupt is generated if INEA = 1. TINT is

READ/CLEAR ONLY and is set by the MK50H28 and cleared by writing a ”1” into the bit.

Writing a ”0” has no effect. It is also cleared by Bus RESET or by issuing a Stop primitive.

RINT

RECEIVER INTERRUPT is set after the MK50H28 updates an entry in the Receive

Descriptor Ring (this is done once per received frame, not per received buffer). When

RINT is set, an interrupt is generated if INEA = 1. RINT is READ/CLEAR ONLY and is

set by the MK50H28 and cleared by writing a ”1” into the bit. Writing a ”0” has no effect.

It is cleared by Bus RESET or by issuing a Stop primitive.

This bit is READ ONLY and will always read as zero.

MK50H28

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